Analog capacitor on submicron pitch metal level

Patent metadata

Field	Value
Publication number	US-10608075-B2
Application number	US-201916240194-A
Country	US
Kind code	B2
Filing date	Jan 4, 2019
Priority date	Oct 25, 2017
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a capacitor located over a semiconductor substrate, the capacitor comprising:
a first conductive layer having a first lateral perimeter;
a second conductive layer having a second smaller lateral perimeter;
a first dielectric layer located between the second conductive layer and the first conductive layer, the first dielectric layer having a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter;

an interconnect line located over the substrate, the interconnect line comprising:
a third conductive layer being about coplanar with and having about a same thickness as the first conductive layer; and
a second dielectric layer located over the third conductive layer, being about coplanar with and having about a same thickness as the thinner portion of the first dielectric layer.

2. The integrated circuit of claim 1 , further comprising a third dielectric layer having the first lateral perimeter located between the first conductive layer and the first dielectric layer, and a fourth dielectric layer located between the third conductive layer and the second dielectric layer, the fourth dielectric layer being about coplanar with and having about a same thickness as the third dielectric layer.

3. The integrated circuit of claim 1 , further comprising a transistor formed on or over the semiconductor substrate, and a first via connecting a first terminal of the transistor to the first conductive layer.

4. The integrated circuit of claim 3 , further comprising a second via connecting a second terminal of the transistor to the third conductive layer.

5. The integrated circuit of claim 1 , wherein the thicker portion has a thickness in a range between about 8 nm and about 12 nm, and the thinner portion has a thickness of at least about 3 nm.

6. The integrated circuit of claim 1 , wherein the first conductive layer includes a layer comprising a nitride of titanium or of tantalum located on a layer comprising aluminum.

7. The integrated circuit of claim 1 , wherein the second conductive layer has a thickness in a range from about 100 nm to about 150 nm, and includes a nitride of titanium or of tantalum.

8. The integrated circuit of claim 1 , wherein the interconnect line is a first interconnect line, and further comprising a second interconnect line, the second interconnect line having a fourth conductive layer about coplanar with the first and third conductive layers, the second interconnect line having a linewidth and being laterally spaced apart from the first interconnect line by a space width, a sum of the linewidth and the space width being less than about 420 nm.

9. The integrated circuit of claim 1 , further comprising:
a second interconnect line located over the capacitor, and a first via connecting the second interconnect line to the second conductive layer;
a third interconnect line located over the first interconnect line, and a second via connecting the third interconnect line to the first interconnect line.

10. The integrated circuit of claim 1 , further comprising:
a third dielectric layer located between the first conductive layer and the first dielectric layer, and a fourth dielectric layer located between the first conductive layer and the third dielectric layer, the first, second, third and fourth dielectric layers comprising silicon and oxygen, and the first and fourth dielectric layers having a lower nitrogen concentration than the third dielectric layer.

11. The integrated circuit of claim 1 , wherein the third dielectric layer has a thickness in a range between about 20 nm and about 30 nm.

12. The integrated circuit of claim 1 , further comprising a first via that connects directly to the second conductive layer, and a second via extending through the thinner portion and connecting directly to the first conductive layer.

13. A method of forming an integrated circuit, comprising:
forming a first conductive layer having a first lateral perimeter;
forming a second conductive layer over the first dielectric layer, the second conductive layer having a second smaller lateral perimeter;
forming a first dielectric layer located between the second conductive layer and the first conductive layer, the first dielectric layer having a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter;
forming an interconnect line located over the substrate, the interconnect line comprising a third conductive layer being about coplanar with and having about a same thickness as the first conductive layer; and
forming a second dielectric layer located over the third conductive layer, being about coplanar with and having about a same thickness as the thinner portion of the first dielectric layer.

14. The method of claim 13 , further comprising forming a transistor on or over the semiconductor substrate, and connecting a first terminal of the transistor to the first conductive layer.

15. The method of claim 14 , further comprising connecting a second terminal of the transistor to the third conductive layer.

16. The method of claim 13 , wherein the thicker portion has a thickness in a range between about 8 nm and about 12 nm, and the thinner portion has a thickness of at least about 3 nm.

17. The method of claim 13 , wherein the first conductive layer includes a layer comprising a nitride of titanium or of tantalum located on a layer comprising aluminum.

18. The method of claim 13 , wherein the second conductive layer has a thickness in a range from about 100 nm to about 150 nm, and includes a nitride of titanium or of tantalum.

19. The method of claim 13 , wherein the interconnect line is a first interconnect line, and further comprising forming a second interconnect line having a linewidth and being about coplanar with and laterally spaced apart from the first interconnect line by a space width, a sum of the linewidth and the space width being less than about 420 nm.

20. The method of claim 13 , wherein the interconnect line is a first interconnect line, and further comprising:
forming a second interconnect line located over the second conductive layer, and a first via connecting the second interconnect line to the second conductive layer;
forming a third interconnect line located over the first interconnect line, and a second via connecting the third interconnect line to the first interconnect line.

21. The method of claim 13 , further comprising:
forming a third dielectric layer between the first dielectric layer and the first conductive layer, the first, second and fifth dielectric layers comprising silicon and oxygen, the first and second dielectric layers having a lower nitrogen concentration than the first dielectric layer.

22. The method of claim 13 , wherein the third dielectric layer has a thickness in a range between about 20 nm and about 30 nm.

23. The method of claim 13 , further comprising forming a first via that connects directly to the second conductive layer, and forming a second via extending through the thinner portion and connecting directly to the first conductive layer.

Assignees

• Texas Instruments Inc

Inventors

• Srinivasan Bhaskar
• Mathur Guru
• Meisner Stephen Arlon
• Chang Shih Chang
• Gagnet Corinne Ann

Classifications

• H01L29/1608

  Electricity · mapped topic

• H01L27/0629

  Electricity · mapped topic

• H01L21/0276

  Electricity · mapped topic

• H01L29/94

  Electricity · mapped topic

• H01L23/5223

  Electricity · mapped topic