Firmware or hardware component assist for memory mapped I/O

Patent metadata

Field	Value
Publication number	US-10606759-B2
Application number	US-201715407621-A
Country	US
Kind code	B2
Filing date	Jan 17, 2017
Priority date	Jan 17, 2017
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

A method is provided for providing access to a data block in a device of a processing system. The device is connected to a processor of the processing system via an extension bus, and the processing system includes a memory connected to the processor via a memory bus, an operating system and hardware and/or firmware components for controlling access to the device. The method includes adding by the operating system for the data block a first entry in a page table of the processing system. The added entry represents the data block. A memory management unit (MMU) of the processing system may receive a request of the data block. Upon receiving the request, the MMU may instruct one of the hardware or firmware components to provide access to the data block using the added entry.

First claim

What is claimed is:

1. A method comprising:
establishing a page table within a processing system which comprises an entry having a page table entry structure with a physical address field for a data block indicative of a physical address of the data block;
providing access to a further data block in a device of the processing system, the device being connected to a processor of the processing system via an extension bus, the processing system also comprising a memory connected to the processor via a memory bus, the processing system further including one or more components for controlling access to the device, the processing system comprising an operating system, wherein the providing comprises:
adding by the operating system for the further data block a special entry in the page table of the processing system, the added special entry representing the further data block and the added special entry having a special page table entry format with no physical address indication for the data block, the special page table entry format of the added special entry being a different format than a format of the page table entry structure of the entry in the page table;
receiving by a memory management unit (MMU) of the processing system a request of the further data block; and
based on the added special entry, instructing by the MMU one component of the one or more components to provide access to the further data block using the added special entry in the page table by generating an address where the further data block is stored in the device.

2. The method of claim 1 , further comprising upon receiving the request, checking by the MMU the page table for determining that the special entry represents the requested further data block.

3. The method of claim 2 , wherein the MMU comprises a translation lookaside buffer (TLB), and based on receiving the request, the providing further comprises determining whether an entry of the TLB corresponds to the further data block, and based on detecting a TLB miss for the requested further data block, performing the checking.

4. The method of claim 3 , further comprising controlling the MMU for preventing creation of an entry in the TLB indicating the further data block.

5. The method of claim 1 , further comprising upon receiving the request:
determining whether the special entry represents the further data block;
based on determining that the special entry represents the further data block creating a TLB entry comprising the special entry in a TLB of the MMU, triggering a repeating of the receiving; and
wherein the instructing is performed based on identifying in the TLB the special entry that represents the further data block.

6. The method of claim 1 , wherein instructing the one or more components further comprises:
using the special entry for generating the address where the further data block is stored in the device;
performing a first reading of the further data block from the device using the generated address;
loading the read data block into the memory; and
performing a second reading of the further data block from the memory.

7. The method of claim 6 , wherein the first reading is performed via a PCI host bridge (PHB) of the processing system.

8. The method of claim 1 , wherein adding the special entry comprises:
sending by the operating system a request to the one component for adding the special entry; and
adding the special entry upon receiving an acknowledgment from the one component, wherein the added special entry comprises information on the sender of the acknowledgement.

9. The method of claim 1 , wherein adding the special entry comprises:
registering by the operating system with the one component of the one or more components of the processing system the special entry to be added;
adding the special entry upon receiving a confirmation from the one component of the one or more components.

10. The method of claim 1 , wherein the added entry indicates at least one of:
the added special entry is a valid or invalid entry;
the one component;
the further data block being a read only data block; or
storage characteristics for storing the further data block, the storage characteristics comprising at least one of storage technology for storing the further data block, copy on write, read/write/execute permissions, locking in the device.

11. The method of claim 10 , further comprising selecting the one component using the information stored in the added special entry.

12. The method of claim 1 , wherein the operating system comprises a hypervisor.

13. The method of claim 1 , wherein the one component comprises at least one hardware or firmware component of the one or more components.

14. A system for facilitating access to a data block, the system comprising:
a memory; and
a processor communicatively coupled with the memory, wherein the system performs a method comprising:
establishing a page table within a processing system which comprises an entry having a page table entry structure with a physical address field for a data block indicative of a physical address of the data block;
providing access to a further data block in a device of the processing system, the device being connected to a processor of the processing system via an extension bus, the processing system also comprising a memory connected to the processor via a memory bus, the processing system further including one or more components for controlling access to the device, the processing system comprising an operating system, wherein the providing comprises:
adding by the operating system for the further data block a special entry in the page table of the processing system, the added special entry representing the further data block and the added special entry having a special page table entry format with no physical address indication for the data block, the special page table entry format of the added special entry being a different format than a format of the page table entry structure of the entry in the page table;
receiving by a memory management unit (MMU) of the processing system a request of the further data block; and
based on the added special entry, instructing by the MMU one component of the one or more components to provide access to the further data block using the added special entry in the page table by generating an address where the further data block is stored in the device.

15. The system of claim 14 , further comprising upon receiving the request, checking by the MMU the page table for determining that the special entry represents the requested further data block.

16. The system of claim 15 , wherein the MMU comprises a translation lookaside buffer (TLB), and based on receiving the request, the providing further comprises determining whether an entry of the TLB corresponds to the further data block, and based on detecting a TLB miss for the requested further data block, performing the checking.

17. The system of claim 16 , further comprising controlling the MMU for preventing creation of an entry in the TLB indicating the further data block.

18. The system of claim 14 , further comprising upon receiving the request:
determining whether the special entry represents the further data block;
based on determining that the special entry represents the further data block, creating a TLB entry comprising the special entry in a TLB of the MMU, triggering a repeating of the receiving; and
wherein the instructing is performed based on identifying in the TLB the special entry that represents the further data blo

Assignees

• IBM

Inventors

• Kraemer Marco
• Otte Carsten
• Raisch Christoph

Classifications

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0665

  at area level, e.g. provisioning of virtual or logical volumes · CPC title

• G06F2212/152

  Virtualized environment, e.g. logically partitioned system · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title