Energy-aware power sharing control

Patent metadata

Field	Value
Publication number	US-10606338-B2
Application number	US-201715859265-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	Dec 29, 2017
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

Aspects of the embodiments are directed to systems, methods, and program products for rebalancing power in a multi-chip computing platform, which includes a core processor and a discrete peripheral processor. Embodiments include determining that the core processor and the discrete peripheral processor are in a limited usage state; altering a polling interval of the core processor and the discrete peripheral processor from a first polling time to a second polling time, the second polling time greater than the first polling time; and polling the core processor and the discrete peripheral processor after an expiration of the second polling time. Embodiments also include using thermal and/or energy consumption data to dynamically adjust polling times to permit the core processor and the discrete peripheral processor to remain in an idle or low power state for as long as possible.

First claim

What is claimed is:

1. A computer program product comprising one or more tangible computer-readable non-transitory storage media comprising computer-executable instructions operable to, when executed by at least one computer processor, cause the at least one computer processor to implement operations at a multi-chip computing platform that includes a core processor and a discrete peripheral processor, the operations comprising:
determining that the core processor and the discrete peripheral processor are in a limited usage state;
altering a polling interval of the core processor and the discrete peripheral processor from a first polling time to a second polling time, the second polling time greater than the first polling time; and
polling the core processor and the discrete peripheral processor after an expiration of the second polling time;
wherein the operation of determining that the core processor and the discrete peripheral processor are in a limited usage state comprises:
determining that the multi-chip platform is in a limited usage mode;
determining that a core processor utilization is less than a predetermined threshold utilization value; and
determining that a discrete peripheral processor utilization is less than a predetermined threshold value

wherein the operation of determining that the core processor and the discrete peripheral processor are in a limited usage state comprises determining that a multi-chip platform power is less than a threshold power level (ewmaMCPPower[t]<MCPPowerThreshold).

2. The computer program product of claim 1 , wherein the operation of determining that the multi-chip platform is in a limited usage mode comprises:
determining that a proportional-integral-derivative (PID) controller budget (PIDBudget[t]) for power headroom of the multi-chip platform is less than zero (PIDBudget[t]<0) or that an exponential weighted moving average (EWMA) of a PIDBudget slope is negative (ewmaPIDBudgetSlope[t]<0).

3. The computer program product of claim 1 , the operations further comprising:
measuring a thermal output of one or both of the core processor or the discrete peripheral processor by a thermal sensor;
determining that the thermal output is greater than a thermal value level threshold;
polling one or both of the core processor or the discrete peripheral processor for power resource consumption; and
altering the polling interval to the first polling time.

4. The computer program product of claim 3 , wherein the thermal value level threshold is a first thermal value level threshold; the operations further comprising:
determining that the thermal output is greater than a second thermal value level threshold, the second thermal value level threshold lower than the first thermal value level threshold;
polling one or both of the core processor or the discrete peripheral processor for power resource consumption; and
altering the polling interval to a third polling time, the third polling time greater than the first polling time and less than the second polling time.

5. The computer program product of claim 1 , the operations further comprising:
measuring a power consumption of one or both of the core processor or the discrete peripheral processor;
determining that the power consumption is greater than a threshold power consumption value level;
polling one or both of the core processor or the discrete peripheral processor for power resource allocation; and
altering the polling interval to the first polling time.

6. The computer program product of claim 5 , wherein the operation of determining that the power consumption is greater than a power consumption value level threshold comprises:
associating an energy unit with a counter value and a portion of an energy metric;
determining an energy based on a determined power consumption and a power consumption time;
determining a counter value for the determined energy;
increasing a current counter value with the determined counter value; and
correlating the increased counter with an energy metric.

7. The computer program product of claim 5 , wherein the power consumption value level threshold is a first power consumption value level threshold; the operations further comprising:
determining that the power consumption is greater than a second power consumption value level threshold, the second power consumption value level threshold lower than the first power consumption value level threshold; polling one or both of the core processor or the discrete peripheral processor for power resource consumption; and
altering the polling interval to a third polling time, the third polling time greater than the first polling time and less than the second polling time.

8. A multi-chip computing platform comprising:
processing circuitry;
a discrete peripheral processor;
a memory for storing instructions and accessible by the processing circuitry, the processing circuitry to perform the instructions to:
determine that the core processor and the discrete peripheral processor are in a limited usage state;
alter a polling interval of the core processor and the discrete peripheral processor from a first polling time to a second polling time, the second polling time greater than the first polling time; and
poll the core processor and the discrete peripheral processor after an expiration of the second polling time;
wherein the processing circuitry is further to perform the instructions to:
determine that the multi-chip platform is in a limited usage mode;
determine that a core processor utilization is less than a predetermined threshold utilization value; and
determine that a discrete peripheral processor utilization is less than a predetermined threshold value;
wherein the operation of determining that the core processor and the discrete peripheral processor are in a limited usage state comprises determining that a multi-chip platform power is less than a threshold power level (ewmaMCPPower[t]<MCPPowerThreshold).

9. The multi-chip computing platform of claim 8 , wherein the processing circuitry is further to perform the instructions to:
measure a thermal output of one or both of the core processor or the discrete peripheral processor by a thermal sensor;
determine that the thermal output is greater than a thermal value level threshold;
poll one or both of the core processor or the discrete peripheral processor for power resource consumption; and
alter the polling interval to the first polling time.

10. The multi-chip computing platform of claim 9 , wherein the thermal value level threshold is a first thermal value level threshold, wherein the processing circuitry is further to perform the instructions to:
determine that the thermal is greater than a second thermal value level threshold, the second thermal value level threshold lower than the first thermal value level threshold; poll one or both of the core processor or the discrete peripheral processor for power resource consumption; and
alter the polling interval to a third polling time, the third polling time greater than the first polling time and less than the second polling time.

11. The multi-chip computing platform of claim 8 , wherein the processing circuitry is further to perform the instructions to:
measure a power consumption of one or both of the core processor or the discrete peripheral processor;
determine that the power consumption is greater than a threshold power consumption value level;
poll one or both of the core processor or the discrete peripheral processor for power resource allocation; and
alter the polling interval to the first polling time.

12. The multi-chip computing platform of cl

Assignees

• Intel Corp

Inventors

• Nair Sudheer
• Hermerding Ii James G
• Ananthakrishnan Avinash

Classifications

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/206 Primary

  comprising thermal management · CPC title

• G06F1/3293 Primary

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title