Neutral point clamped multiple-level switching unit for voltage inverter or rectifier

Patent metadata

Field	Value
Publication number	US-10601341-B2
Application number	US-201816184953-A
Country	US
Kind code	B2
Filing date	Nov 8, 2018
Priority date	Nov 10, 2017
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

A neutral point clamped multiple-level switching unit is disclosed, including four series-connected switches, where the electric path in the four switches approximately follows a T shape, two of the switches located in the middle of the series association being arranged in the foot of the T.

First claim

What is claimed is:

1. A neutral point clamped multiple-level switching unit comprising four series-connected switches (K 1 , K 2 , K 3 , K 4 ), wherein an electric path in the four series-connected switches approximately follows a T shape, two (K 2 , K 3 ) of the switches located in the middle of the series-connected switches being arranged in a foot of the T shape, each of said two switches (K 2 , K 3 ) is series-connected with a first and a second diode (Dh, Dl) respectively, between a first output terminal ( 15 ) and a second output terminal ( 17 ) of the neutral point clamped multiple-level switching unit,
the unit being formed on at least one printed circuit wafer ( 60 , 61 , 62 ) defining conductive areas for receiving components and contact transfer wires, the at least one printed circuit wafer comprising two coplanar wafers ( 61 , 62 ) respectively receiving at least the first and second switches (K 1 , K 2 ) and the third and fourth switches (K 3 , K 4 ), each of the two coplanar wafers comprising a conductive area ( 612 , 617 ) defining one of the separate nodes ( 171 , 172 ) of the connection of one of the first and second diodes (Dh, Dl);
wherein a node between said two switches defines the first output terminal ( 15 ) of the neutral point clamped multiple-level switching unit,
and wherein:
the four series-connected switches are connected between two input terminals ( 11 , 13 ) of the unit;
a node ( 16 ) between a first switch (K 1 ) and a second switch (K 2 ) is coupled, by the first diode (Dh), to the second output terminal ( 17 ) of the neutral point clamped multiple-level switching unit;
a node ( 18 ) between a third switch (K 3 ) and a fourth switch (K 4 ) is coupled, by the second diode (Dl), to the second output terminal ( 17 ) of the unit, said two switches being the second and third switches; and
the first and second diodes (Dh, Dl) are connected to the separate nodes ( 171 , 172 ) that are interconnected to the second output terminal ( 17 ).

2. The unit of claim 1 , wherein said two switches (K 2 , K 3 ) are arranged to, when said two switches conduct a same current, mutually compensate (MI) respective parasitic inductances of said two switches.

3. The unit of claim 1 , wherein first surfaces of the series-connected switches (K 1 , K 2 , K 3 , K 4 ) and the first and second diodes (Dh, Dl) are coplanar.

4. The unit of claim 3 , wherein four conductive areas ( 611 , 616 , 615 , 618 ) each support one of the series-connected switches (K 1 , K 2 , K 3 , K 4 ).

5. The unit of claim 1 , wherein each of the series-connected switches (K 1 , K 2 , K 3 , K 4 ) is respectively associated with a diode (D 1 , D 2 , D 3 , D 4 ) assembled in parallel.

6. The unit of claim 1 , wherein the series-connected switches (K 1 , K 2 , K 3 , K 4 ) are semiconductor components, preferably MOS or IGBT transistors.

7. The unit of claim 5 , wherein each diode (D 1 , D 2 , D 3 , D 4 ) assembled in parallel with one of the series-connected switches (K 1 , K 2 , K 3 , K 4 ) is an intrinsic diode of die series-connected switch.

8. The unit of claim 1 , wherein each of the series-connected switches (K 1 , K 2 , K 3 , K 4 ) is formed of a plurality of semiconductor chips electrically in parallel.

9. A power converter comprising:
at least one neutral point clamped multiple-level switching unit ( 1 ) of claim 1 ; and
at least one capacitive dividing bridge (C 1 , C 2 ).

10. The converter of claim 9 , wherein the capacitive dividing bridge comprises two capacitive elements (C 1 , C 2 ) series-connected between input terminals ( 11 , 13 ), a node ( 12 ) between the two capacitive elements being coupled to the second, output terminal ( 17 ).

Assignees

• Commissariat Energie Atomique

Inventors

• Lefevre Guillaume

Classifications

• H02M1/44

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• H02M7/003

  Constructional details, e.g. physical layout, assembly, wiring or busbar connections · CPC title

• H02M7/487 Primary

  Neutral point clamped inverters · CPC title

• H02M7/537

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title

• H02M2007/4835

  Electricity · mapped topic