Display panel comprising a wire disposed and sandwiched in between a sealant and a planarization layer and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9581871-B2
Application number	US-201414279321-A
Country	US
Kind code	B2
Filing date	May 16, 2014
Priority date	May 16, 2013
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A display panel, including a device substrate, an opposite substrate, a sealant, and a display medium, is provided. A pixel array of the device substrate is located in a display region, and a periphery circuit of the device substrate is located in a non-display region, wherein the periphery circuit includes at least one driving device, a planarization layer, and at least one wire. The planarization layer covers the driving device. The wire is located on the planarization layer, and the wire is electrically connected with the driving device and disposed to overlap the driving device. The opposite substrate is located opposite to the device substrate, and the sealant is located in the non-display region therebetween and covers the wire. The display medium is located between the device substrate, the opposite substrate, and the sealant. A manufacturing method of a display panel is also provided.

First claim

What is claimed is:

1. A display panel, having a display region and a non-display region, the display panel comprising:
a device substrate, comprising a substrate and a pixel array and a periphery circuit disposed on the substrate, wherein the pixel array is located in the display region and the periphery circuit is located in the non-display region, and the periphery circuit comprises:
at least one driving device;
a planarization layer covering the driving device; and
at least one wire located on the planarization layer, wherein the wire and the driving device are electrically connected with each other and overlapped each other;

an opposite substrate located opposite to the device substrate;
a sealant located in the non-display region between the device substrate and the opposite substrate to assemble the device substrate and the opposite substrate together, wherein the sealant covers the wire of the device substrate, and the wire is disposed and sandwiched in between the sealant and the planarization layer; and
a display medium located between the device substrate, the opposite substrate, and the sealant.

2. The display panel according to claim 1 , wherein the planarization layer comprises an organic material, and a thickness of the planarization layer is substantially 2˜3 micrometers.

3. The display panel according to claim 1 , wherein the sealant comprises a light curing adhesive material.

4. The display panel according to claim 1 , further comprising a protection layer covering the wire and located between the planarization layer and the sealant.

5. The display panel according to claim 4 , wherein the protection layer comprises an inorganic dielectric material.

6. The display panel according to claim 1 , wherein the driving device comprises at least one thin film transistor and at least one capacitor, and the wire and the thin film transistor are electrically connected with each other.

7. The display panel according to claim 1 , wherein the pixel array comprises a thin film transistor array and a pixel electrode electrically connected with the thin film transistor array, the planarization layer covers the thin film transistor array, and the pixel electrode is located on the planarization layer.

8. The display panel according to claim 1 , wherein a width of the non-display region is substantially 1000˜1500 micrometers.

9. A method for manufacturing the display panel according to claim 1 , the method comprising:
providing the substrate having the display region and the non-display region;
forming a thin film transistor array in the display region of the substrate and simultaneously forming the driving device in the non-display region of the substrate;
forming the planarization layer to cover the thin film transistor array and the driving device;
forming a pixel electrode on the planarization layer in the display region, and the pixel electrode being electrically connected with the thin film transistor array to form the pixel array;
forming the wire on the planarization layer in the non-display region, wherein the wire and the driving device overlap each other and are electrically connected with each other;
forming the sealant on the planarization layer to cover the wire, such that the wire is disposed and sandwiched in between the sealant and the planarization layer; and
assembling the opposite substrate and the substrate together by the sealant, and forming the display medium between the opposite substrate, the substrate, and the sealant.

10. The manufacturing method according to claim 9 , wherein the planarization layer comprises an organic material, and a thickness of the planarization layer is substantially 2˜3 micrometers.

11. The manufacturing method according to claim 9 , further comprising performing an irradiation process on the sealant to cure the sealant.

12. The manufacturing method according to claim 9 , further comprising forming a protection layer on the wire to cover the wire after forming the wire.

13. The manufacturing method according to claim 12 , wherein the protection layer comprises an inorganic dielectric material.

14. The manufacturing method according to claim 9 , wherein the driving device comprises at least one thin film transistor and at least one capacitor, and the wire and the thin film transistor are electrically connected with each other.

Assignees

• Au Optronics Corp

Inventors

• Hsu Wen-Yi
• Chen Maw-Song

Classifications

• G02F1/13458 Primary

  Terminal pads · CPC title

• G02F1/13454

  Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence) · CPC title