Flip chip backside mechanical die grounding techniques

Patent metadata

Field	Value
Publication number	US-10600753-B2
Application number	US-201615249424-A
Country	US
Kind code	B2
Filing date	Aug 28, 2016
Priority date	Aug 28, 2015
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

A semiconductor device includes an integrated circuit attached to a chip carrier in a flip chip configuration. A substrate extends to a back surface of the integrated circuit, and an interconnect region extends to a front surface of the integrated circuit. A substrate bond pad is disposed at the front surface, and is electrically coupled through the interconnect region to the semiconductor material. The chip carrier includes a substrate lead at a front surface of the chip carrier. The substrate lead is electrically coupled to the substrate bond pad. An electrically conductive compression sheet is disposed on the back surface of the integrated circuit, with lower compression tips making electrical contact with the semiconductor material in the substrate. The electrically conductive compression sheet is electrically coupled to the substrate lead of the chip carrier by a back surface shunt disposed outside of the integrated circuit.

First claim

What is claimed is:

1. An integrated circuit (IC) package comprising:
a semiconductor die including a first side and a second side opposite the first side, the first side including active circuitry;
a sheet attached to the second side, the sheet including a tip that electrically connects with the second side; and
a lid attached to a substrate, and contacting the sheet;
wherein the tip includes two parallel surfaces, and wherein each of the two parallel surfaces forms an acute angle with respect to a plane along a surface of the sheet, and wherein the tip extends from an edge of a hole in the sheet.

2. The IC package of claim 1 , wherein the sheet includes a metal selected from the group consisting of steel and bronze.

3. The IC package of claim 1 , wherein the semiconductor die is attached to the substrate.

4. The IC package of claim 3 , wherein the sheet comprises a shunt portion that connects to a lead of the substrate.

5. The IC package of claim 1 further comprising a heat sink compound between the semiconductor die and the sheet.

6. The IC package of claim 5 , wherein the heat sink compound fills the hole.

7. The IC package of claim 1 , wherein the tip and the hole include one of a triangular shape and a rectangular shape.

8. The IC package of claim 4 , wherein the shunt portion extends only from a portion of a side of the sheet.

9. The IC package of claim 1 , wherein the tip includes a third surface perpendicular to the plane along the surface of the sheet.

10. An integrated circuit (IC) package comprising:
a semiconductor die including a first side and a second side opposite the first side, the first side including active circuitry; and
a sheet attached to the second side, the sheet including a first set of tips extending from edges of a first set of holes, the first set of tips electrically connecting with the second side, the sheet including a second set of tips extending from edges of a second set of holes, the second set of tips extending in a direction opposite to that of the first set of tips, wherein each of the first set of tips and the second set of tips includes two parallel surfaces, and each of the two parallel surfaces forms an acute angle with respect to a corresponding plane along a corresponding surface of the sheet.

11. The IC package of claim 10 further comprising a substrate attached to the first side.

12. The IC package of claim 11 further comprising a lid attached to the substrate, and contacting the second set of tips.

13. The IC package of claim 10 further comprising a heat sink compound between the semiconductor die and the sheet, wherein the heat sink compound contacts the first set of tips, the second set of tips, and fills the first set of holes and the second set of holes.

14. The IC package of claim 11 , wherein the sheet comprises two wing shaped shunt portions that connect to a lead of the substrate, and wherein the two wing shaped shunt portions extend in opposite directions.

15. The IC package of claim 14 , wherein the two wing shaped shunt portions electrically connect to two leads of the substrate.

16. The IC package of claim 14 , wherein the two wing shaped shunt portions are not part of the sheet and are electrically connected to the sheet.

17. The IC package of claim 11 , wherein the first side is electrically connected to the substrate via bump bonds.

18. The IC package of claim 10 , wherein the first set of tips and the first set of holes and the second set of tips and the second set of holes include one of a triangular shape and a rectangular shape.

19. The IC package of claim 10 , wherein a lateral spacing between two adjacent tips of the first set of tips is less than 1 millimeter.

20. The IC package of claim 10 , wherein the semiconductor die includes a plurality of PMOS transistors, a plurality of NMOS transistors and an interconnect region.

Assignees

• Texas Instruments Inc

Inventors

• Salzman James Fred

Classifications

• H01L2924/00014

  Electricity · mapped topic

• H01L2224/2957

  Electricity · mapped topic

• H01L24/29

  Electricity · mapped topic

• H01L23/492

  Electricity · mapped topic

• H01L2224/29124

  Electricity · mapped topic