Semiconductor package

Patent metadata

Field	Value
Publication number	US-10600729-B2
Application number	US-201916359307-A
Country	US
Kind code	B2
Filing date	Mar 20, 2019
Priority date	May 16, 2017
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

A semiconductor package includes a substrate, a first semiconductor chip and a second semiconductor chip adjacent to each other on the substrate, and a plurality of bumps on lower surfaces of the first and second semiconductor chips. The first and second semiconductor chips have facing first side surfaces and second side surfaces opposite to the first side surfaces. The bumps are arranged at a higher density in first regions adjacent to the first side surfaces than in second regions adjacent to the second side surfaces.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a substrate;
at least two semiconductor chips on the substrate;
a plurality of bumps on lower surfaces of respective ones of the at least two semiconductor chips, the plurality of bumps being arranged at a higher density in adjacent regions of the at least two semiconductor chips than in other regions of the at least two semiconductor chips; and
at least one insulating layer between the substrate and each of the at least two semiconductor chips to fill between the plurality of bumps, the at least one insulating layer having a volume in a region between the at least two semiconductor chips that is smaller than a volume in a region outside non-adjacent side surfaces of the at least two semiconductor chips.

2. The semiconductor package as claimed in claim 1 , wherein the at least one insulating layer protrudes outward from the non-adjacent side surfaces of the at least two semiconductor chips farther than from adjacent side surfaces of the at least two semiconductor chips.

3. The semiconductor package as claimed in claim 2 , wherein the at least one insulating layer protrudes from other side surfaces of the at least two semiconductor chips connecting respective ones of the adjacent side surfaces and the non-adjacent side surfaces, and
a protrusion distance from the other side surfaces of the at least two semiconductor chips is greater than a protursion distance from the adjacent side surfaces of the at least two semiconductor chips.

4. The semiconductor package as claimed in claim 1 , wherein the at least one insulating layer protrudes from the non-adjacent side surfaces of the at least two semiconductor chips without protruding from adjacent side surfaces of the at least two semiconductor chips.

5. The semiconductor package as claimed in claim 1 , wherein the at least one insulating layer protrudes from adjacent side surfaces of the at least two semiconductor chips without covering the adjacent side surfaces of the at least two semiconductor chips.

6. The semiconductor package as claimed in claim 1 , wherein the at least one insulating layer protrudes from side surfaces of the at least two semiconductor chips farther than from corner portions of the at least two semiconductor chips.

7. The semiconductor package as claimed in claim 1 , wherein the at least one insulating layer protrudes only from side surfaces of the at least two semiconductor chips without protruding from corner portions of the at least two semiconductor chips.

8. The semiconductor package as claimed in claim 1 , wherein the at least two semiconductor chips includes different types of semiconductor chips.

9. The semiconductor package as claimed in claim 8 , wherein the at least two semiconductor chips includes a logic chip and a memory chip.

10. The semiconductor package as claimed in claim 1 , wherein the substrate is an interposer.

11. The semiconductor package as claimed in claim 1 , further comprising:
a lower substrate below the substrate; and
at least one lower semiconductor chip on the lower substrate.

12. The semiconductor package as claimed in claim 11 , further comprising solder balls on a lower surface of the substrate,
wherein the at least two semiconductor chips and the at least one lower semiconductor chip are electrically connected through the solder balls and the substrate.

13. The semiconductor package as claimed in claim 1 , wherein the at least two semiconductor chips includes a first semiconductor chip and two second semiconductor chips disposed one side of the first semiconductor chip in parallel, and
the plurality of bumps on lower surfaces of the second semiconductor chips are arranged at a higher density in adjacent regions to the first semiconductor chips.

14. A semiconductor package, comprising:
a substrate;
a first semiconductor chip and a second semiconductor chip adjacent to each other on the substrate, the first and second semiconductor chips having facing first side surfaces and second side surfaces opposite to respective ones of the first side surfaces;
a plurality of bumps on lower surfaces of respective ones of the first and second semiconductor chips, the plurality of bumps being arranged at a higher density in first regions of respective ones of the first and second semiconductor chips than in second regions of respective ones of the first and second semiconductor chips, the first regions of the first and second semiconductor chips being adjacent to the first side surfaces of the first and second semiconductor chips, respectively, and the second regions of the first and second semiconductor chips being adjacent to the second side surfaces of the first and second semiconductor chips, respectively; and
insulating layers between the substrate and each of the first and the second semiconductor chips, each of the insulating layers having a volume in a region between the first and second semiconductor chips that is smaller than a volume in a region outside the second side surfaces of the first and second semiconductor chips, respectively.

15. The semiconductor package as claimed in claim 14 , wherein the insulating layers protrude outward from the second side surfaces of the first and second semiconductor chips farther than from respective ones of the first side surfaces.

16. The semiconductor package as claimed in claim 14 , wherein the insulating layers protrude from the first side surfaces of of the first and second semiconductor chips without covering the first side surfaces.

17. The semiconductor package as claimed in claim 14 , wherein the insulating layers protrude from side surfaces including the first and second side surfaces of the first and second semiconductor chips farther than from corner portions of the first and second semiconductor chips.

18. The semiconductor package as claimed in claim 14 , wherein the insulating layers having a higher thermal expansion coefficient than each of the first and second semiconductor chips.

19. The semiconductor package as claimed in claim 14 , wherein the plurality of bumps on the lower surface of the first semiconductor chip have a substantially same size, and the plurality of bumps on the lower surface of the second semiconductor chip have a substantially same size.

20. The semiconductor package as claimed in claim 14 , further comprising support bumps in the second regions, each one of the support bumps having a greater size than each of the plurality of bumps.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Kyong Soon
• Lee Jae Eun

Classifications

• H01L2224/73103

  Electricity · mapped topic

• H01L2224/13109

  Electricity · mapped topic

• H01L2224/11452

  Electricity · mapped topic

• H01L24/91

  Electricity · mapped topic

• H01L2224/05569

  Electricity · mapped topic