Methods of forming staircase structures

Patent metadata

Field	Value
Publication number	US-10600681-B2
Application number	US-201816164542-A
Country	US
Kind code	B2
Filing date	Oct 18, 2018
Priority date	Dec 29, 2017
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.

First claim

What is claimed is:

1. A staircase structure, comprising:
opposing tiers of alternating insulative levels and conductive levels or alternating insulative levels and nitride materials, the tiers comprising a stepped profile; and
at least three portions of a fill material between the opposing tiers, the at least three portions of the fill material comprising different material compositions.

2. The staircase structure of claim 1 , wherein the at least three portions of the fill material comprise at least three portions of different dielectric materials.

3. The staircase structure of claim 1 , wherein each of the at least three portions of the fill material comprises a material independently selected from the group consisting of a silicon oxide, a silicon nitride, or a metal oxide.

4. A semiconductor device, comprising:
a staircase structure comprising opposing tiers of alternating insulative levels and conductive levels, the opposing tiers comprising a stepped profile and at least three portions of a fill material in a valley between the opposing tiers, the at least three portions of the fill material comprising the same material composition and different dopant concentrations.

5. The staircase structure of claim 4 , wherein the fill material comprises at least three portions of a silicon oxide material.

6. The semiconductor device of claim 4 , wherein the stepped profile of the opposing tiers comprises stairs exhibiting different riser heights and substantially the same tread width.

7. The semiconductor device of claim 4 , wherein the stepped profile of the opposing tiers comprises stairs exhibiting substantially the same riser height and substantially the same tread width.

8. The semiconductor device of claim 4 , wherein the stepped profile of the opposing tiers comprises stairs exhibiting different riser heights and different tread widths.

9. The semiconductor device of claim 4 , wherein the stepped profile of the opposing tiers comprises stairs exhibiting substantially the same riser height and different tread widths.

10. The semiconductor device of claim 4 , wherein each of the at least three portions of the fill material comprises a silicon oxide material and each of the at least three portions is formulated to exhibit a different etch selectivity.

11. The semiconductor device of claim 10 , wherein each of the at least three portions of the fill material comprises the silicon oxide material and a dopant comprising boron, phosphorus, arsenic, or aluminum oxide.

12. A semiconductor device, comprising:
stairs of a staircase structure, opposing stairs of the staircase structure separated by at least three portions of a fill material, the at least three portions of the fill material comprising the same material composition and different material qualities.

13. The semiconductor device of claim 12 , wherein each of the stairs comprises a tread width corresponding to a thickness of at least two of the at least three portions of the fill material.

14. The semiconductor device of claim 12 , wherein the stairs comprise a graduated tread width, a smaller tread width of the stairs proximal to a lowermost stair of the stairs and a larger tread width proximal to an uppermost stair of the stairs.

15. The semiconductor device of claim 12 , wherein the stairs comprise a smaller tread width proximal to a base material of the staircase structure and a larger tread width distal to the base material.

16. The semiconductor device of claim 12 , wherein an uppermost stair of the stairs comprises a wider tread width than a lowermost stair of the stairs.

17. The semiconductor device of claim 12 , wherein upper surfaces of the at least three portions of the fill material are substantially coplanar with upper surfaces of the staircase structure.

18. The semiconductor device of claim 12 , wherein the fill material comprises a substantially uniform width.

19. A staircase structure, comprising:
opposing tiers of alternating insulative levels and conductive levels, the tiers comprising a stepped profile; and
at least three portions of a fill material between the opposing tiers, the at least three portions comprising the same material composition and different crystalline structures.

Assignees

• Micron Technology Inc

Inventors

• Williamson Lance
• Olson Adam L
• Jain Kaveri
• Dembi Robert
• Brown William R

Classifications

• H01L21/76877

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic