Memory device

Patent metadata

Field	Value
Publication number	US-10600453-B2
Application number	US-201816130034-A
Country	US
Kind code	B2
Filing date	Sep 13, 2018
Priority date	Feb 19, 2018
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

A memory device includes a memory cell array including a plurality of memory cells, a page buffer unit including the plurality of memory cells, and a driving determination unit determining whether to perform at least one of a pre-charging operation, a development operation and a latching operation of page buffers connected to the memory cells provided with the read voltage.

First claim

What is claimed is:

1. A memory device, including:
a memory cell array including a plurality of memory cells;
a plurality of page buffers configured to store data associated with memory cells of the plurality of memory cells that are provided with a read voltage; and
processing circuitry configured to,
select some of the plurality of page buffers as selected page buffers such that remaining ones of the plurality of page buffers are non-selected page buffers such that at least one of the plurality of page buffers are the non-selected page buffers,
perform at least one of a pre-charging operation, a development operation, and a latching operation of the selected page buffers connected to the memory cells provided with the read voltage such that such that the non-selected page buffers are non-actuated in synchronization with the at least one of the pre-charging operation, the development operation, and the latching operation of the selected page buffers.

2. The memory device of claim 1 , wherein the processing circuitry is configured to select some of the plurality of the page buffers such that bit lines connected to the selected page buffers are arranged consecutively.

3. The memory device of claim 1 , wherein the processing circuitry is configured to select some of the plurality of the page buffers such that bit lines connected to the selected page buffers are spaced apart from each other by an interval.

4. The memory device of claim 1 , wherein the processing circuitry is configured to select some of the plurality of the page buffers such that the processing circuitry is configured to pre-charge bit lines connected to the selected page buffers, and to terminate pre-charging of bit lines connected to the non-selected page buffers.

5. The memory device of claim 1 , wherein the processing circuitry is configured to develop sensing nodes associated with the selected page buffers, and to terminate development of sensing nodes associated with the non-selected page buffers.

6. The memory device of claim 1 , wherein the processing circuitry is configured to provide a latch control signal to latches associated with the selected page buffers, and to terminate providing the latch control signal to latches of the non-selected page buffers.

7. The memory device of claim 1 , wherein the processing circuitry is configured to sample the data stored in the selected page buffers.

8. A memory device, comprising;
a plurality of page buffers configured to store data associated with memory cells among a plurality of memory cells provided with a read voltage, and output the data stored in the plurality of page buffers; and
processing circuitry configured to,
count at least one of on-cells and off-cells of the memory cells based on the data output from ones of the plurality of page buffers for calculating fail bit value,
determine which of the plurality of page buffers are selected page buffers, and
drive the selected page buffers.

9. The memory device of claim 8 , wherein the plurality of page buffers are configured to sequentially outputs data stored therein.

10. The memory device of claim 9 , wherein the processing circuitry is configured to count the data output from the selected page buffers.

11. The memory device of claim 9 , wherein the selected page buffers are configured to perform one or more of a pre-charging operation, a development operation and a latching operation.

12. The memory device of claim 11 , wherein non-selected page buffers of the plurality of the page buffers are configured to terminate performing at least one of the pre-charging operation, the development operation and the latching operation.

13. A memory device comprising;
a memory cell array including a plurality of memory cells; and
a plurality of pages buffers configured to store data associated with memory cells among the plurality of memory cells provided with a read voltage, and to sample the data stored in selected page buffers among the plurality of page buffers such that non-selected page buffers among the plurality of page buffers including at least one of the plurality of page buffers are non-actuated in synchronization with sampling of the data.

14. The memory device of claim 13 , wherein the memory device is configured to terminate a pre-charging operation of bit lines connected to the non-selected page buffers.

15. The memory device of claim 13 , wherein the memory device is configured to terminate a development operation of sensing nodes associated with the non-selected page buffers.

16. The memory device of claim 13 , wherein the memory device is configured to terminate a latching operation of latches provided in the non-selected page buffers.

17. The memory device of claim 13 , wherein the memory device is configured to sequentially sample the selected page buffers.

18. The memory device of claim 13 , further comprising:
processing circuitry configured to count at least one of on-cells and off-cells of the memory cells based on the data that is output from the selected page buffers.

19. The memory device of claim 18 , wherein the processing circuitry is configured to calculate a bit fail value by counting at least one of the on-cells or off-cells.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Han Jun
• Kwak Dong Hun
• Lee Yo Han

Classifications

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C7/1048 Primary

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G06F12/0882

  Page mode · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title