Memory device, memory system, and method of controlling read voltage of the memory device

Patent metadata

Field	Value
Publication number	US-9685206-B2
Application number	US-201313948557-A
Country	US
Kind code	B2
Filing date	Jul 23, 2013
Priority date	Jul 23, 2012
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively. The memory device further includes a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array comprising a plurality of memory cells;
a page buffer unit comprising a plurality of page buffers, each of the plurality of page buffers configured to store a plurality of pieces of data sequentially read at different read voltages from a memory cell among the plurality of memory cells, and each configured to perform a logic operation on the plurality of pieces of data stored therein and to output a corresponding logic result;
a counting unit configured to count a number of memory cells read by the plurality of page buffers that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation output by each of the page buffers; and
a valley detecting unit configured to detect a read voltage level that corresponds to a valley between two adjacent states of the memory cells based on the number of the memory cells counted by the counting unit.

2. The memory device of claim 1 , wherein the logic operation is an XOR operation, and each of the plurality of page buffers performs the XOR operation on two pieces of data which are respectively read at two read voltage levels that are adjacent to each other from among the different read voltage levels, and
the counting unit counts the number of ‘1’ outcomes resulting from the XOR operation with respect to each of the plurality of sections.

3. The memory device of claim 1 , wherein the counting unit comprises counters corresponding to a number of sectors or pages of the memory cell array on which a read operation is performed.

4. The memory device of claim 1 , wherein the different read voltage levels are automatically updated in the memory device.

5. The memory device of claim 1 , further comprising a voltage level determining unit configured to determine the different read voltage levels applied to the memory cell array.

6. The memory device of claim 5 , wherein the voltage level determining unit comprises:
a start voltage storage unit configured to store a start read voltage that is applied to the memory cell array;
an offset storage unit configured to store a plurality of offset voltages that are pre-defined; and
an adding unit configured to add one of the plurality of offset voltages to the start read voltage.

7. The memory device of claim 6 , wherein the start voltage storage unit stores a digital value of the start read voltage,
the offset storage unit stores digital values of the plurality of offset voltages, and
the voltage level determining unit further comprises a voltage level generating unit configured to generate an analog voltage level from an output of the adding unit.

8. The memory device of claim 6 , wherein the start read voltage is determined to vary with respect to different memory chips.

9. The memory device of claim 6 , wherein the plurality of offset voltages are determined to be the same with respect to different memory chips.

10. The memory device of claim 1 , wherein the valley detecting unit comprises:
a minimum value storage unit configured to store a minimum value of the numbers of the memory cells that exist in each of the plurality of sections; and
a minimum offset storage unit configured to store an offset as a minimum offset, wherein the offset corresponds to a section that is from among the plurality of sections and that has the minimum value.

11. The memory device of claim 10 , wherein the valley detecting unit further comprises a valley storage unit configured to store a read voltage level corresponding to the valley based on the minimum offset stored in the minimum offset storage unit.

12. The memory device of claim 11 , wherein the valley storage unit comprises a plurality of valley storage devices, and
the number of the plurality of valley storage devices corresponds to the number of valleys between the two adjacent states of the memory cells.

13. The memory device of claim 1 , further comprising a read voltage generating unit configured to provide the memory cell array with a read voltage level corresponding to the valley detected by the valley detecting unit.

14. The memory device of claim 13 , wherein the read voltage generating unit comprises:
an initial read voltage storage unit configured to store a plurality of initial read voltages that respectively correspond to valleys between two adjacent states from among a plurality of states of the memory cells;
an offset storage unit configured to store a plurality of offsets that correspond to the valleys, respectively; and
an adding unit configured to add one of the plurality of offsets to one of the plurality of initial read voltages.

15. The memory device of claim 14 , wherein the read voltage generating unit further comprises:
a first control unit configured to control the initial read voltage storage unit to select one of the plurality of initial read voltages stored in the initial read voltage storage unit; and
a second control unit configured to control the offset storage unit to use one of the plurality of offsets stored in the offset storage unit so as to generate a read voltage.

16. The memory device of claim 14 , wherein the initial read voltage storage unit stores digital values of the plurality of initial read voltages, the offset storage unit stores digital values of the plurality of offsets, and
the read voltage generating unit further comprises a voltage level generating unit configured to generate an analog voltage level from an output from the adding unit.

17. The memory device of claim 1 , further comprising a pre-charge determining unit configured to determine whether to pre-charge at least one bitline connected to at least one memory cell from among the plurality of memory cells,
wherein the at least one memory cell is a memory cell of which a read voltage is already determined or is a memory cell of which the read voltage is not required to be detected.

18. The memory device of claim 1 , further comprising a sampling unit configured to control the page buffer unit to perform sampling on at least one memory cell from among the plurality of memory cells and to perform an operation to determine a read voltage based on the sampled at least one memory cell.

19. A memory device, comprising:
a memory cell array comprising a plurality of bit lines and word lines, and a plurality of memory cells located at intersections of the bit lines and word lines, each of the memory cells programmable between at least 2 threshold voltage states;
a read voltage generator configured to apply a read voltage to selected word lines of the memory cell array;
a page buffer unit comprising a plurality of page buffers respectively connected to the bit lines of the memory cell array;
a counter; and
a logic circuit configured to execute a minimal error search (MES) operation, the MES operation including controlling the read voltage generator to sequentially apply different read voltages to the selected word lines, controlling the page buffers to perform logic operations on respective read results stored for each of a plurality of memory cells, the read results respectively corresponding to at least two of the sequentially applied different read voltages, and controlling the counter to count results of the logic operations,
wherein the different read voltages are in a vicinity between adjacent threshold voltages of adjacent threshold voltage states, and wherein the count results are indicative of a read voltage resulting in a minimal read error between the ad

Assignees

• Choi Myung-Hoon
• Jeong Jae-Yong
• Park Ki-Tae
• Samsung Electronics Co Ltd

Inventors

• Choi Myung-Hoon
• Jeong Jae-Yong
• Park Ki-Tae

Classifications

• G11C16/3431

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title

• G11C11/5642 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G11C16/00

  Erasable programmable read-only memories (G11C14/00 takes precedence) · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title