Method for driving a pixel circuit, display panel and display device

Patent metadata

Field	Value
Publication number	US-10600353-B2
Application number	US-201815912045-A
Country	US
Kind code	B2
Filing date	Mar 5, 2018
Priority date	Sep 30, 2017
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

Disclosed are a method for driving a pixel circuit, a display panel and a display device. The pixel circuit includes: a data write module, a drive transistor, a hold module and a light-emitting element. The method comprises, in a time period for a frame of display: a data writing stage in which a data signal is written by the data write module into a gate electrode of the drive transistor; a light-emitting stage in which a voltage on the gate electrode of the drive transistor is held by the hold module, the drive transistor supplies a drive current to the light-emitting element, and the light-emitting element emits light in response to the drive current; and a cut-off stage in which the drive transistor operates in a full cut-off region.

First claim

What is claimed is:

1. A method for driving a pixel circuit, wherein
the pixel circuit comprises: a data write module, a drive transistor, a hold module and a light-emitting element, wherein the drive method comprises, in a time period for a frame of display:
a data writing stage wherein a data signal is written by the data write module into a gate electrode of the drive transistor;
a light-emitting stage wherein a voltage on the gate electrode of the drive transistor is held by the hold module, the drive transistor supplies a drive current to the light-emitting element, and the light-emitting element emits light in response to the drive current; and
a cut-off stage wherein the drive transistor operates in a full cut-off region;
wherein the pixel circuit further comprises a threshold compensation module, a reset module, a first light-emitting control module and a second light-emitting control module;
wherein a control terminal of the data write module is electrically connected with a first scan line, a first terminal of the data write module is electrically connected with a data line, and a second terminal of the data write module is electrically connected with a first electrode of the drive transistor;
wherein a control terminal of the threshold compensation module is electrically connected with the first scan line, a first terminal of the threshold compensation module is electrically connected with a second electrode of the drive transistor, and a second terminal of the threshold compensation module is electrically connected with the gate electrode of the drive transistor;
wherein a first terminal of the hold module is electrically connected with the gate electrode of the drive transistor, and a second terminal of the hold module is connected with a first level signal line;
wherein a control terminal of the first light-emitting control module is electrically connected with a first light-emitting signal line, a first terminal of the first light-emitting control module is electrically connected with the first level signal line, and a second terminal of the first light-emitting control module is electrically connected with the first electrode of the drive transistor;
wherein a control terminal of the second light-emitting control module is electrically connected with the first light-emitting signal line, a first terminal of the second light-emitting control module is electrically connected with the second electrode of the drive transistor, and a second terminal of the second light-emitting control module is electrically connected with a first electrode of the light-emitting element;
wherein a control terminal of the reset module is electrically connected with a second scan line, a first terminal of the reset module is electrically connected with a third level signal line, and a second terminal of the reset module is electrically connected with the gate electrode of the drive transistor;
wherein a second electrode of the light-emitting element is electrically connected with a second level signal line;
wherein the method further comprises a reset stage, wherein in the reset stage, the reset module is turned on so that a reset signal on the third level signal line is written into the gate electrode of the drive transistor;
wherein in the data writing stage, the reset module is turned off, and the data write module and the threshold compensation module are turned on, so that the voltage associated with the threshold voltage of the drive transistor is stored by the holding module; and
wherein in the light-emitting stage, the first light-emitting control module and the second light-emitting control module are turned on, so that the drive current generated by the drive transistor is transmitted to the light-emitting element.

2. The method for driving a pixel circuit as claimed in claim 1 , wherein the drive transistor is one of an N-type transistor and a P-type transistor;
when the drive transistor is an N-type transistor, then in the cut-off stage, a voltage difference between the gate electrode and a source electrode of the drive transistor will be smaller than a negative value of the threshold voltage; or
when the drive transistor is a P-type transistor, then in the cut-off stage, the voltage difference between the gate electrode and the source electrode of the drive transistor will be larger than the negative value of the threshold voltage thereof.

3. The method for driving a pixel circuit as in claim 1 ,
wherein the cut-off stage is arranged before the light-emitting stage or after the light-emitting stage.

4. The method for driving a pixel circuit as claimed in claim 1 ,
wherein the proportion of the cut-off stage in a time period for a frame of display is greater than zero and less than or equal to 5%.

5. The method as claimed in claim 1 ,
wherein the signal on the third level signal line further comprises a cut-off voltage signal; and
wherein during the cut-off stage, the reset module is turned on, the cut-off voltage signal on the third level signal line is written into the gate electrode of the drive transistor, the first light-emitting control module is turned on, and the first level signal on the first level signal line is written into the first electrode of the driver transistor.

6. The method as claimed in claim 5 , wherein
during the turned-on state of the reset module, the cut-off voltage signal and the reset signal are in turn written into the gate electrode of the drive transistor.

7. The method as claimed in claim 1 ,
wherein the reset stage is arranged before the light-emitting stage, and the cut-off stage is arranged after the light-emitting stage; and
wherein in the cut-off stage, the first light-emitting control module and the second light-emitting control module are turned off and the reset module is turned on, and the cut-off voltage signal on the third level signal line is written into the gate electrode of the drive transistor.

8. The method as claimed in claim 7 , wherein
the cut-off stage of each row of the pixel circuits is located at the end of a time period for a frame of display, and the cut-off stage of each row of the pixel circuits is arranged after the light-emitting stage of the last row of the pixel circuits.

9. The method as claimed in claim 7 , wherein
in the cut-off stage, each of the first light-emitting control module and the second light-emitting control module of each row of the pixel circuits is turned off, each of the reset module, the data write module and the threshold compensation module of each row of the pixel circuits is turned on, and the cut-off voltage signal on the third level signal line is written into the gate electrode of the drive transistor of each row of the pixel circuits.

10. The method as claimed in claim 1 , wherein
the signal on the first scan line and the signal on the second scan line are both pulse signals, and the signal on the second scan line occurs before the signal on the first scan line occurs.

11. The method as claimed in claim 1 , wherein
the signal on the third level signal line comprises at least one pulse signal, and the pulse signal comprises a high level stage and a low level stage, and
wherein the high level stage is used for one of the reset signal and the cut-off signal, and the low level stage is used for the other of the reset signal and the cut-off signal.

12. The method as claimed in claim 11 , wherein
the difference between the voltage value of the high level stage and the voltage value of the first level signal is greater than the negative value of the threshold voltage of the drive transistor.

13. The method as claimed in claim 1

Assignees

• Shanghai Tianma Am Oled Co Ltd

Inventors

• Xi Kerui
• Cui Tingting
• Lin Baiquan
• Ouyang Junting
• Cai Zhonglan

Classifications

• G09G2310/0264

  Details of driving circuits · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2310/0251

  Precharge or discharge of pixel before applying new pixel voltage · CPC title