Surface-emitting semiconductor laser device and method for producing the same
US-2016099549-A1 · Apr 7, 2016 · US
US10594110B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10594110-B2 |
| Application number | US-201816189794-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 13, 2018 |
| Priority date | Nov 16, 2017 |
| Publication date | Mar 17, 2020 |
| Grant date | Mar 17, 2020 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A vertical cavity surface emitting laser includes: a supporting base having a principal surface including III-V compound semiconductor containing gallium and arsenic as constituent elements; and a post disposed on the principal surface. The post has a lower spacer region including a III-V compound semiconductor containing gallium and arsenic as group-III elements, and an active layer having a quantum well structure disposed on the lower spacer region. The quantum well structure has a concentration of carbon in a range of 2×10 16 cm −3 or more to 5×10 16 cm −3 or less. The quantum well structure includes a well layer and a barrier layer. The well layer includes a III-V compound semiconductor containing indium as a group-III element, and the barrier layer includes a III-V compound semiconductor containing indium and aluminum as group-III elements. The lower spacer region is disposed between the supporting base and the active layer.
Opening claim text (preview).
What is claimed is: 1. A vertical cavity surface emitting laser comprising: a supporting base having a principal surface including III-V compound semiconductor containing gallium and arsenic as constituent elements; and a post disposed on the principal surface, the post having a lower spacer region and an active layer, the lower spacer region including III-V compound semiconductor containing gallium and arsenic as group-III elements, the active layer having a quantum well structure disposed on the lower spacer region, the quantum well structure having a concentration of carbon in a range of 2×10 16 cm −3 or more to 5×10 16 cm −3 or less, the quantum well structure including a well layer and a barrier layer, the well layer including III-V compound semiconductor containing indium as a group-III element, the barrier layer including III-V compound semiconductor containing indium and aluminum as group-III elements, and the lower spacer region being disposed between the supporting base and the active layer. 2. The vertical cavity surface emitting laser according to claim 1 , further comprising a lower laminate having semiconductor layers for a lower Bragg distributed reflector disposed on the supporting base, the principal surface of the supporting base including GaAs, the lower laminate being disposed between the lower spacer region and the supporting base, the lower spacer region being in contact with the lower laminate, and the III-V compound semiconductor of the lower spacer region including an AlGaAs layer in contact with the active layer. 3. The vertical cavity surface emitting laser according to claim 1 , wherein the quantum well structure has an AlGaInAs well layer and an AlGaAs barrier layer. 4. A method for fabricating a vertical cavity surface emitting laser comprising: preparing a substrate including III-V compound semiconductor containing gallium and arsenic as constituent elements; growing a semiconductor laminate for a lower Bragg distributed reflector on a principal surface of the substrate at a substrate temperature of 670 degrees Celsius or more; supplying a raw material containing organometallic material to a growth reactor to grow a first semiconductor layer on the semiconductor laminate at a substrate temperature of 590 degrees Celsius or less, the first semiconductor layer containing aluminum as a group-III constituent element and not containing indium as a group-III constituent element; and supplying a raw material containing organometallic material to a growth reactor to grow a second semiconductor layer for an active layer on the first semiconductor layer at a substrate temperature of 590 degrees Celsius or less, the second semiconductor layer containing indium as a group-III constituent element. 5. The method according to claim 4 , wherein the active layer has a concentration of carbon ranging from 2×10 16 cm −3 to 5×10 16 cm −3 .
Mesa comprising active layer · CPC title
Electrodes, e.g. characterised by the structure · CPC title
doping of barrier layers that confine charge carriers in the laser structure, e.g. the barriers in a quantum well structure (barriers in quantum wells per se H01S5/3407) · CPC title
with a well layer having only As as V-compound, e.g. AlGaAs, InGaAs · CPC title
AIIIBV compounds · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.