Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-10593801-B2
Application number	US-201615062553-A
Country	US
Kind code	B2
Filing date	Mar 7, 2016
Priority date	Apr 10, 2015
Publication date	Mar 17, 2020
Grant date	Mar 17, 2020

Abstract

Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
providing a substrate including an active pattern and a mask pattern sequentially stacked on the substrate, the active pattern protruding from the substrate, and the mask pattern overlapping an uppermost surface of the active pattern;
forming a first liner layer on the substrate to cover the active pattern and the mask pattern;
forming a field isolation insulating layer on the first liner layer;
etching the field isolation insulating layer, the first liner layer, and the mask pattern to expose an upper portion, including the uppermost surface, of the active pattern and to form a field isolation pattern that exposes the upper portion of the active pattern and covers a lower portion of the active pattern;
forming a second liner layer on the upper portion of the active pattern and the field isolation pattern;
forming a dummy gate on the second liner layer and crossing the active pattern;
forming spacer patterns on sidewalls of the dummy gate, respectively, and on the second liner layer;
forming source/drain patterns on the active pattern adjacent the sidewalls of the dummy gate, respectively;
etching the second liner layer which is formed on the active pattern and is not covered by the dummy gate and the spacer patterns;
forming an interlayer insulating layer on the field isolation pattern and the active pattern on the sidewalls of the dummy gate;
forming an opening in the interlayer insulating layer by removing the dummy gate;
forming a gate insulating pattern in the opening; and
forming a gate pattern on the gate insulating pattern in the opening,
wherein the active pattern includes germanium, and the source/drain patterns have a germanium content greater than a germanium content of the active pattern, and
wherein each of the source/drain patterns directly contacts both the second liner layer and a respective one of the spacer patterns.

2. The method of claim 1 , wherein the second liner layer includes a high-k dielectric material.

3. The method of claim 1 , wherein forming the opening comprises:
exposing the second liner layer by removing the dummy gate; and
etching the exposed second liner layer such that a portion of the second liner layer remains under one of the spacer patterns.

4. The method of claim 1 , wherein forming the opening comprises exposing the second liner layer by removing the dummy gate, and wherein forming the gate insulating pattern comprises forming the gate insulating pattern on the second liner layer.

5. The method of claim 1 , wherein forming the source/drain patterns comprises:
forming epitaxial layers on the active pattern adjacent the sidewalls of the dummy gate, respectively.

6. The method of claim 5 , further comprising forming an etch stop layer on the second liner layer,
wherein forming the dummy gate comprises forming the dummy gate on the etch stop layer, and the dummy gate crosses the active pattern and the field isolation pattern,
wherein forming the spacer patterns comprises forming the spacer patterns on the sidewalls of the dummy gate and the etch stop layer, and
wherein etching the second liner layer comprises etching the etch stop layer and the second liner layer using the dummy gate and the spacer patterns as an etch mask.

7. A method of fabricating a semiconductor device, the method comprising:
forming a trench in a substrate to form an active pattern;
forming a first liner layer extending on the active pattern;
forming a field isolation layer on the first liner layer;
forming a field isolation pattern and a first liner pattern by etching the field isolation layer and the first liner layer, respectively, wherein etching the field isolation layer and the first liner layer comprises exposing an upper portion, including an uppermost surface, of the active pattern underlying the first liner layer and forming the first liner pattern on a lower portion of the active pattern, and wherein the upper portion of the active pattern is exposed by the field isolation pattern;
after forming the field isolation pattern and the first liner pattern, forming a second liner pattern and a spacer pattern on the active pattern, the spacer pattern overlapping the second liner pattern;
forming a source/drain pattern on the active pattern adjacent the spacer pattern;
forming a gate insulating pattern on the upper portion of the active pattern; and
forming a gate pattern on the gate insulating pattern and crossing the active pattern, the spacer pattern being on a sidewall of the gate pattern,
wherein the second liner pattern includes a high-k dielectric material,
wherein the second liner pattern is self-aligned with the spacer pattern, and
wherein the source/drain pattern directly contacts both the spacer pattern and the second liner pattern and has a germanium content greater than a germanium content of the active pattern.

8. The method of claim 7 , wherein forming the second liner pattern comprises:
forming a second liner layer on the upper portion of the active pattern;
forming a dummy gate on the second liner layer and crossing the active pattern;
forming the spacer pattern on a sidewall of the dummy gate;
removing a first portion of the second liner layer exposed by the dummy gate and the spacer pattern;
forming the source/drain pattern adjacent the sidewall of the dummy gate;
forming an interlayer insulating layer covering the source/drain pattern and exposing the dummy gate;
removing the dummy gate to expose a second portion of the second liner layer; and
etching the second portion of the second liner layer to expose the upper portion of the active pattern such that the second liner pattern is formed under the spacer pattern.

9. The method of claim 8 , wherein the gate insulating pattern is formed on the exposed upper portion of the active pattern to contact the spacer pattern and the second liner pattern.

10. The method of claim 7 , further comprising forming an etch stop layer, wherein the etch stop layer is between the spacer pattern and the second liner pattern.

11. The method of claim 7 ,
wherein the substrate comprises a first region, a second region, and a third region,
wherein forming the trench in the substrate comprises forming a plurality of trenches in the substrate to form a first active pattern protruding from the first region and a second active pattern protruding from the second region,
wherein forming the first liner pattern comprises forming a plurality of first liner patterns in the plurality of trenches, respectively, a first one of the plurality of first liner patterns is on a side of a lower portion of the first active pattern and exposes an upper portion of the first active pattern, and a second one of the plurality of first liner patterns is on a side of a lower portion of the second active pattern and exposes an upper portion of the second active pattern,
wherein forming the field isolation pattern comprises forming a plurality of field isolation patterns in the plurality of trenches, respectively, a first one of the plurality of field isolation patterns covers the side of the lower portion of the first active pattern, and a second one of the plurality of field isolation patterns covers the side of the lower portion of the second active pattern,
wherein the second liner pattern and the spacer pattern are formed on the first active pattern, and the second liner pattern is between the spacer pattern and the first active pattern,
wherein the source/drain pattern is formed on the first active pattern adjacent the spacer pattern,
wherein the germanium content of the source/drain pattern is greater t

Assignees

• Lee Tae Jong
• Hong Sanghyuk
• Kwon Taeyong
• Kim Sunjung
• Kim Cheol
• Samsung Electronics Co Ltd

Inventors

• Lee Tae-Jong
• Hong Sanghyuk
• Kwon Taeyong
• Kim Sunjung
• Kim Cheol

Classifications

• H01L21/823821

  Electricity · mapped topic

• H01L21/823878

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/7848 Primary

  Electricity · mapped topic

• H01L29/161

  Electricity · mapped topic