Display panel and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-10593739-B2
Application number	US-201816133404-A
Country	US
Kind code	B2
Filing date	Sep 17, 2018
Priority date	Dec 8, 2017
Publication date	Mar 17, 2020
Grant date	Mar 17, 2020

Abstract

A method of fabricating a display panel may include forming an oxide semiconductor pattern on a base layer including a first region and a second region, etching first, second, and third insulating layers to form a first groove that overlaps the second region, forming electrodes on the third insulating layer, forming a fourth insulating layer on the third insulating layer to cover the electrodes, thermally treating the fourth insulating layer, forming an organic layer to cover the fourth insulating layer, and forming an organic light emitting diode on the organic layer.

First claim

What is claimed is:

1. A method of fabricating a display panel, comprising:
forming a silicon semiconductor pattern on a base layer including a first region and a second region that is extended from the first region, the silicon semiconductor pattern overlapping the first region;
forming a first control electrode on the silicon semiconductor pattern, the first control electrode overlapping the silicon semiconductor pattern with a first insulating layer interposed therebetween;
forming a second control electrode to overlap the first region and to be spaced apart from the first control electrode with a second insulating layer interposed therebetween;
forming an oxide semiconductor pattern on the second control electrode to overlap the second control electrode with a third insulating layer interposed therebetween;
etching the first, second, and third insulating layers to form a first contact hole and a second contact hole exposing at least a portion of the silicon semiconductor pattern and a first groove that overlaps the second region;
forming on the third insulating layer a first input electrode and a first output electrode that are connected to the silicon semiconductor pattern through the first and second contact holes, and a second input electrode and a second output electrode that are connected to the oxide semiconductor pattern;
forming a fourth insulating layer on the third insulating layer to cover the first input electrode, the first output electrode, the second input electrode, and the second output electrode;
thermally treating the fourth insulating layer at a controlled temperature prior to forming any layer on the fourth insulating layer;
forming an organic layer to cover the fourth insulating layer; and
forming on the organic layer an organic light emitting diode that is connected to the first output electrode.

2. The method of claim 1 , wherein the thermal treating of the fourth insulating layer is performed at a temperature of about 300° C. or higher.

3. The method of claim 2 , wherein the organic layer comprises polyimide.

4. The method of claim 1 , wherein the etching of the first, second, and third insulating layers is performed to simultaneously form the first and second contact holes and the first groove using a single mask.

5. The method of claim 1 , further comprising forming a second groove that overlaps the first groove in the fourth insulating layer after the forming of the fourth insulating layer,
wherein the organic layer is formed to fill the first groove and the second groove.

6. The method of claim 5 , further comprising forming an inorganic layer between the first insulating layer and the base layer,
wherein the forming of the second groove comprises forming a third groove that overlaps the first groove in the inorganic layer.

7. The method of claim 1 , further comprising:
forming a third contact hole in the organic layer to expose a portion of the first output electrode;
forming a connection electrode on the organic layer to be connected to the first output electrode through the third contact hole; and
forming an upper organic layer on the organic layer to cover the connection electrode,
wherein the organic light emitting diode is connected to the connection electrode through the upper organic layer.

8. The method of claim 7 , wherein the connection electrode is formed of a material that is different from the first output electrode.

9. The method of claim 8 , wherein the connection electrode is formed of a material whose resistance is lower than that of the first output electrode.

10. The method of claim 1 , wherein the forming of the first input electrode, the first output electrode, the second input electrode, and the second output electrode comprises:
forming a conductive layer on the third insulating layer to cover the oxide semiconductor pattern; and
patterning the conductive layer using an etching gas,
wherein the etching gas contains a fluoro compound.

11. The method of claim 10 , wherein the conductive layer has a higher etch rate than the oxide semiconductor pattern in the patterning of the conductive layer using the etching gas.

12. A display panel, comprising:
a base layer including a first region and a second region that is bent from the first region along a predetermined bending axis;
a first thin-film transistor provided in the first region, the first thin-film transistor comprising a crystalline silicon semiconductor pattern, a first control electrode, and a first input electrode and a first output electrode that are coupled to the crystalline silicon semiconductor pattern and are spaced apart from each other with the first control electrode interposed therebetween;
a second thin-film transistor disposed in the first region to have a bottom gate structure, the second thin-film transistor comprising a second control electrode, an oxide semiconductor pattern disposed on the second control electrode, and a second input electrode and a second output electrode that are in contact with the oxide semiconductor pattern and are spaced apart from each other;
a passivation layer disposed in the first region and the second region to cover the first thin-film transistor and the second thin-film transistor and to include a first groove that overlaps the second region;
a plurality of inorganic layers disposed between the passivation layer and the base layer to include a second groove that overlaps the first groove;
an organic layer disposed in the first region and the second region and on the passivation layer to cover inner surfaces of the first and second grooves; and
an organic light emitting diode disposed on the organic layer and in the first region and electrically connected to the first thin-film transistor,
wherein a plurality of inorganic layers are disposed to expose a portion of a top surface of the base layer, and the organic layer is disposed to be in contact with the portion of the top surface of the base layer.

13. The display panel of claim 12 , wherein the second input electrode and the second output electrode comprise molybdenum.

14. The display panel of claim 12 , further comprising:
an upper organic layer disposed between the organic layer and the organic light emitting diode; and
a connection electrode disposed between the upper organic layer and the organic layer and coupled to each of the organic light emitting diode and the first output electrode,
wherein the connection electrode comprises a material that is different from that of the first output electrode.

15. The display panel of claim 14 , wherein the connection electrode comprises a material whose resistance is lower than that of the first output electrode.

16. The display panel of claim 14 , further comprising a signal line disposed in the second region and overlapping the first groove and the second groove,
wherein the signal line is disposed on the same layer as the connection electrode.

17. The display panel of claim 12 , further comprising a pixel definition layer disposed on the organic layer and including an opening,
wherein the organic light emitting diode is disposed in the opening,
wherein the pixel definition layer overlaps the first region and the second region and comprises an organic material.

18. The display panel of claim 17 , wherein the pixel definition layer further comprises a recessed portion on an inner surface of the opening.

19. The display panel of claim 12 , wherein the passivation layer is in contact with the oxide semiconductor pattern.

Assignees

• Samsung Display Co Ltd

Inventors

• SON Kyoungseok
• Kim Myounghwa
• Kim Eoksu
• Kim Taesang
• Kano Masataka

Classifications

• H01L2251/5338

  Electricity · mapped topic

• H01L51/0097

  Electricity · mapped topic

• H01L27/3262

  Electricity · mapped topic

• H01L27/3276

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic