Ferroelectric memory device

Patent metadata

Field	Value
Publication number	US-10593699-B2
Application number	US-201715839849-A
Country	US
Kind code	B2
Filing date	Dec 13, 2017
Priority date	Mar 21, 2017
Publication date	Mar 17, 2020
Grant date	Mar 17, 2020

Abstract

A ferroelectric memory device includes a substrate, a ferroelectric structure having a first ferroelectric material layer, an electrical floating layer, and a second ferroelectric material layer sequentially stacked on the substrate, and a gate electrode layer disposed on the ferroelectric structure. A hysteresis loop of the second ferroelectric material layer differs from a hysteresis loop of the first ferroelectric material layer.

First claim

What is claimed is:

1. A ferroelectric memory device comprising:
a substrate;
a ferroelectric structure disposed on the substrate, wherein the ferroelectric structure comprises
a first ferroelectric material layer disposed on the substrate,
an electrical floating layer disposed on the first ferroelectric material layer, and
a second ferroelectric material layer disposed on the electrical floating layer; and
a gate electrode layer disposed on the ferroelectric structure,
wherein a hysteresis loop of the second ferroelectric material layer differs from a hysteresis loop of the first ferroelectric material layer, and
wherein the first ferroelectric material layer, the electrical floating layer, the second ferroelectric material layer, and the gate electrode layer are sequentially stacked;
wherein the first and second ferroelectric material layers each comprise the same metal oxide and each comprise one or more dopants, and
wherein the one or more dopants of the first ferroelectric material layer differ from the one or more dopants of the second ferroelectric material layer;
wherein the metal oxide comprises at least one of a hafnium oxide, a zirconium oxide, and a hafnium zirconium oxide; and
wherein the electrical floating layer is disposed between the first ferroelectric material layer and the second ferroelectric material layer, and wherein only the first ferroelectric material layer contacts the substrate.

2. The ferroelectric memory device of claim 1 , wherein the one or more dopants comprises at least one selected from a group consisting of carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), and lanthanum (La).

3. The ferroelectric memory device of claim 1 ,
wherein the first and second ferroelectric material layers each comprise a different metal oxide.

4. The ferroelectric memory device of claim 1 ,
wherein a polarization orientation of the second ferroelectric material layer is adjusted from a first level corresponding to a first logic state to a second level corresponding to a second logic state by applying a predetermined write voltage applied to the gate electrode layer such that a write operation to the ferroelectric memory device is performed.

5. The ferroelectric memory device of claim 4 ,
wherein the predetermined write voltage induces an electron distribution in the electrical floating layer that corresponds to the polarization orientation of the second ferroelectric material layer, and
the electron distribution is applied to a polarization orientation of the first ferroelectric material layer.

6. The ferroelectric memory device of claim 1 ,
wherein the ferroelectric structure further comprises an interfacial insulation layer disposed between the substrate and the first ferroelectric material layer.

7. The ferroelectric memory device of claim 1 , further comprising
a source region and a drain region disposed in the substrate at respective sides of the ferroelectric structure.

Assignees

• Sk Hynix Inc

Inventors

• Yoo Hyangkeun

Classifications

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C11/223 Primary

  using MOS with ferroelectric gate insulating film · CPC title

• H01L29/516

  Electricity · mapped topic

• H01L27/1159 Primary

  Electricity · mapped topic

• H01L29/513

  Electricity · mapped topic