Resistive memory device having a trimmable resistance of at least on of a driver and a sinker is trimmed based on a row location

Patent metadata

Field	Value
Publication number	US-9679643-B1
Application number	US-201615065787-A
Country	US
Kind code	B1
Filing date	Mar 9, 2016
Priority date	Mar 9, 2016
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

A device is disclosed that includes a driver, a sinker, a memory column, a reference column, a reference resistor and a sensing unit. At least one of the driver and the sinker has a trimmable resistance. For write operation, one of resistive memory cells is conducted based on a row location in the memory column thereof, the driver provides a write current flowing therethrough and the trimmable resistance is trimmed based on the row location. For read operation, the sensing unit senses a read current of the memory column and a reference current of the reference column and the reference resistor when one of the resistive memory cells and a positionally corresponding one of the reference bit cells are conducted.

First claim

What is claimed is:

1. A device, comprising:
a driver;
a sinker, wherein at least one of the driver and the sinker has a trimmable resistance; and
a memory column comprising a plurality of resistive memory cells each being electrically connected between the driver and the sinker through a first line and a second line respectively;
when one of the resistive memory cells is conducted based on an address decode information that reflects a row location of the conducted resistive memory cell in the memory column, the driver is configured to provide a write current flowing through the first line, the conducted resistive memory cell and the second line to the sinker, and the trimmable resistance is trimmed based on the row location.

2. The device of claim 1 , wherein one of the first line and the second line is a bit line, the other one of the first line and the second line is a source line and each of the resistive memory cells is controlled to be conducted according to a control signal from a word line generated based on the address decode information.

3. The device of claim 1 , wherein the sinker comprises a plurality parallel-connected resistive units having the trimmable resistance such that when the row location of the conducted resistive memory cell in the column is closer to the driver, more of a number of the resistive units is controlled to be conducted to have a lower resistance.

4. The device of claim 3 , wherein the sinker comprises a metal oxide semiconductor (MOS) transistor, a metal resistor, a poly resistor or a combination of the above.

5. The device of claim 1 , wherein the driver comprises a plurality parallel-connected resistive units having the trimmable resistance such that when the row location of the conducted resistive memory cell in the column is closer to the driver, less of a number of the resistive units is controlled to be conducted to have a higher resistance.

6. The device of claim 5 , wherein the driver comprises a metal oxide semiconductor transistor, a metal resistor, a poly resistor or a combination of the above.

7. The device of claim 1 , wherein each of the resistive memory cells is a magnetoresistive random-access memory (MRAM) or a resistive random-access memory (RRAM).

8. The device of claim 1 , wherein the memory column is disposed in a memory array arranged in rows and columns, wherein the memory column is one of the columns and the row location of the conducted resistive memory cell in the memory column corresponds to one of the rows, and each of the first line and the second line are electrically connected to the driver and the sinker through a switch such that the memory column is selected based on the address decode information.

9. A device, comprising:
a memory column comprising a plurality of resistive memory cells;
a reference column comprising a plurality of reference bit cells;
a reference resistor configured to have a reference resistance between a high state resistance and a low state resistance of the resistive memory cells and electrically connected to the reference column; and
a sensing unit configured to sense a read current drained by the memory column and a reference current drained by the reference column and the reference resistor when one of the resistive memory cells and a positionally corresponding one of the reference bit cells are conducted based on an address decode information.

10. The device of claim 9 , the sensing unit further comprises:
a memory driver and a memory sinker, wherein each of the resistive memory cells is electrically connected between the memory driver and a memory sinker through a first memory line and a second memory line;
a reference driver, wherein each of the reference bit cells is electrically connected between the reference driver and the reference resistor through a first reference line and a second reference line;
a memory clamping transistor electrically connected to the first memory line through a memory read node and to the memory driver through a memory sensing node, wherein the memory clamping transistor is configured to clamp the memory read node at a fixed read voltage when the memory driver provides a first current to the first memory line;
a reference clamping transistor electrically connected to the first reference line through a reference read node and to the reference driver through a reference sensing node, wherein the reference clamping transistor is configured to clamp the reference read node at the fixed read voltage when the reference driver provides a second current that is identical to the first current to the first reference line; and
a comparator configured to sense a first voltage and a second voltage at the memory sensing node and the reference sensing node respectively, wherein the read current at the memory sensing node flows through the first memory line, the conducted resistive memory cells, the second memory line and the memory sinker, and the reference current at the reference sensing node flows through the first reference line, the conducted reference bit cells, the second reference line and the reference resistor.

11. The device of claim 10 , wherein the conducted resistive memory cell is determined to have the low state resistance when the comparator determines that the first voltage is smaller than the second voltage, and the conducted resistive memory cell is determined to have the high state resistance when the comparator determines that the first voltage is larger than the second voltage.

12. The device of claim 10 , wherein the reference resistor comprises a metal oxide semiconductor (MOS) resistor conducted in a linear region in response to a driving voltage.

13. The device of claim 12 , further comprising a resistor driving unit comprising:
a driving metal oxide semiconductor resistor identical to the metal oxide semiconductor resistor and conducted in the linear region in response to the driving voltage;
a current source having a same driving ability as the reference driver and configured to provide a current to the driving metal oxide semiconductor resistor through a feedback node; and
a driving comparator to compare a feedback voltage of the feedback node and a preset voltage to generate the driving voltage.

14. The device of claim 10 , wherein the reference resistance is a median value of the high state resistance and the low state resistance.

15. The device of claim 10 , wherein the reference resistor comprises a plurality of parallel-connected metal oxide semiconductor (MOS) resistors, wherein at least one of the metal oxide semiconductor resistors is conducted in a linear region.

16. The device of claim 10 , wherein the memory column is disposed in a memory array arranged in rows and columns, wherein the memory column is one of the columns and each of the resistive memory cells and one of the corresponding reference bit cells correspond to one of the rows, and the memory column is electrically connected to the comparator through a switch such that the memory column is selected based on the address decode information.

17. A method, comprising:
conducting one of a plurality of resistive memory cells in a memory column based on an address decode information that reflects a row location of the conducted resistive memory cell in the memory column, wherein each of the resistive memory cells is electrically connected between a driver and a sinker through a first line and a second line respectively;
trimming a trimmable resistance of at least one of the driver and the sinker based on the address decode information; and
by the driver, providi

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chou Chung-Cheng

Classifications

• G11C2213/82

  Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C2013/0054

  Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title

• G11C13/0033

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C13/0023 Primary

  Address circuits or decoders · CPC title