Radio frequency flash ADC circuits

Patent metadata

Field	Value
Publication number	US-10587281-B2
Application number	US-201816147269-A
Country	US
Kind code	B2
Filing date	Sep 28, 2018
Priority date	Aug 20, 2015
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

A system and method for sampling an RF signal uses a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.

First claim

What is claimed is:

1. A system comprising:
a plurality of preamplifiers, wherein a first input of each of the plurality of preamplifiers is operably coupled to a radio frequency (RF) input, and wherein a second input of each of the plurality of preamplifiers is operably coupled to a reference level of a plurality of reference levels; and
a sampling circuit operably coupled to an output of each of the plurality of preamplifiers, wherein the sampling circuit is operable to produce a plurality of digital outputs.

2. The system of claim 1 , wherein the system comprises a converter operable to convert the plurality of digital outputs to a binary output.

3. The system of claim 1 , wherein the system comprises a series of resistors between a first reference input and a second reference input, each reference level of the plurality of reference levels being produced along the series of resistors.

4. The system of claim 3 , wherein the system comprises a first switch for selecting the first reference input and a second switch for selecting the second reference input.

5. The system of claim 1 , wherein the sampling circuit comprises a plurality of comparators, wherein the output of each of the plurality of preamplifiers is operably coupled to an input of a comparator of the plurality of comparators.

6. The system of claim 1 , wherein the sampling circuit comprises:
a first comparator having a first input and a second input, wherein the first input and the second input are both operably coupled to an output of a first preamplifier of the plurality of preamplifiers; and
a second comparator having a first input operably coupled to the output of the first preamplifier of the plurality of preamplifiers, wherein a second input of the second comparator is operably coupled to an output of a second preamplifier of the plurality of preamplifiers.

7. The system of claim 1 , wherein the sampling circuit comprises:
a first differential amplifier having a first input and a second input operably coupled to an output of a first preamplifier of the plurality of preamplifiers;
a second differential amplifier having a first input operably coupled to the output of the first preamplifier of the plurality of preamplifiers and having a second input operably coupled to an output of a second preamplifier of the plurality of preamplifiers;
a first comparator having a first input and a second input operably coupled to an output of the first differential amplifier; and
a second comparator of the plurality of comparator having a first input operably coupled to the output of the first differential amplifier and having a second input operably coupled to an output of the second differential amplifier.

8. The system of claim 7 , wherein the system comprises a converter operable to convert the plurality of digital outputs to a binary output, each digital output of the plurality of digital outputs being operably coupled to an output from each of the plurality of comparators.

9. The system of claim 1 , wherein the sampling circuit comprises a plurality of comparators, wherein the offset of each comparator of the plurality of comparators is corrected individually using a stored offset value.

10. A method comprising:
receiving, by a first input of each of a plurality of preamplifiers, a radio frequency (RF) input,
receiving, by a second input of each of the plurality of preamplifiers, a respective reference level of a plurality of reference levels; and
producing a plurality of digital outputs by sampling an output of each of the plurality of preamplifiers using a sampling circuit.

11. The method of claim 10 , wherein the method comprises converting the plurality of digital outputs to a binary output.

12. The method of claim 10 , wherein the method comprises generating each reference level of the plurality of reference levels along a series of resistors between a first reference input and a second reference input.

13. The method of claim 12 , wherein the method comprises selecting the first reference input and selecting the second reference input.

14. The method of claim 10 , wherein the sampling circuit comprises a plurality of comparators, wherein the output of each of the plurality of preamplifiers is operably coupled to an input of a comparator of the plurality of comparators.

15. The method of claim 10 , wherein the sampling circuit comprises:
a first comparator having a first input and a second input, wherein the first input and the second input are both operably coupled to an output of a first preamplifier of the plurality of preamplifiers; and
a second comparator having a first input operably coupled to the output of the first preamplifier of the plurality of preamplifiers, wherein a second input of the second comparator is operably coupled to an output of a second preamplifier of the plurality of preamplifiers.

16. The method of claim 10 , wherein the sampling circuit comprises:
a first differential amplifier having a first input and a second input operably coupled to an output of a first preamplifier of the plurality of preamplifiers;
a second differential amplifier having a first input operably coupled to the output of the first preamplifier of the plurality of preamplifiers and having a second input operably coupled to an output of a second preamplifier of the plurality of preamplifiers;
a first comparator having a first input and a second input operably coupled to an output of the first differential amplifier; and
a second comparator of the plurality of comparator having a first input operably coupled to the output of the first differential amplifier and having a second input operably coupled to an output of the second differential amplifier.

17. The method of claim 16 , wherein the method comprises converting the plurality of digital outputs to a binary output, each digital output of the plurality of digital outputs being operably coupled to an output from each of the plurality of comparators.

18. The method of claim 10 , wherein the sampling circuit comprises a plurality of comparators, wherein the offset of each comparator of the plurality of comparators is corrected individually using a stored offset value.

19. The system of claim 18 , wherein the stored offset value is determined according to a counter operably coupled to each comparator output.

20. The method of claim 18 , wherein the method comprises determining the stored offset value according to a counter operably coupled to each comparator output.

Assignees

• Maxlinear Asia Singapore PTE LTD

Inventors

• Lye William Michael
• Zortea Anthony Eugene
• Chana Jatinder

Classifications

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• H03M1/1023

  Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03K5/249

  using clock signals · CPC title

• H03M1/204

  in which one or more virtual intermediate reference signals are generated between adjacent original reference signals, e.g. by connecting pre-amplifier outputs to multiple comparators · CPC title

• H03M1/365

  the voltage divider being a single resistor string · CPC title