Radio frequency flash ADC circuits

Patent metadata

Field	Value
Publication number	US-9847788-B2
Application number	US-201615241526-A
Country	US
Kind code	B2
Filing date	Aug 19, 2016
Priority date	Aug 20, 2015
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A system for sampling an RF signal comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.

First claim

What is claimed is:

1. A system for sampling an RF signal, the system comprising:
a plurality of capacitors, a first port of each of the plurality of capacitors being operably coupled to the RF signal;
a plurality of resistors, a first port of each of the plurality of resistors being operably coupled to a reference level of a plurality of reference levels, a second port of each of the plurality of resistors being operably coupled to a second port of each of the plurality of capacitors; and
a sampling circuit operably coupled to the second port of each of the plurality of resistors, the sampling circuit producing a plurality of digital outputs.

2. The system of claim 1 , wherein the system comprises a converter operable to convert the plurality of digital outputs to a binary output.

3. The system of claim 1 , wherein the system comprises a series of resistors between a first reference input and a second reference input, each reference level of the plurality of reference levels being produced along the series of resistors.

4. The system of claim 3 , wherein the system comprises a first switch for selecting the first reference input and a second switch for selecting the second reference input.

5. The system of claim 1 , wherein the sampling circuit comprises a plurality of comparators, the second port of each of the plurality of resistors being operably coupled to an input of a comparator of the plurality of comparators.

6. The system of claim 1 , wherein the sampling circuit comprises a plurality of comparators, a first comparator of the plurality of comparators having a first input and a second input, each operably coupled to a second port of a first resistor of the plurality of resistors, a second comparator of the plurality of comparators having a first input operably coupled to the second port of the first resistor of the plurality of resistors and having a second input operably coupled to a second port of a second resistor of the plurality of resistors.

7. The system of claim 1 , wherein the sampling circuit comprises a plurality of differential amplifiers and a plurality of comparators, a first differential amplifier of the plurality of differential amplifiers having a first input and a second input operably coupled to a second port of a first resistor of the plurality of resistors, a second differential amplifier of the plurality of differential amplifiers having a first input operably coupled to the second port of the first resistor of the plurality of resistors and having a second input operably coupled to a second port of a second resistor of the plurality of resistors, a first comparator of the plurality of comparators having a first input and a second input operably coupled to an output of the first differential amplifier, a second comparator of the plurality of comparator having a first input operably coupled to the output of the first differential amplifier and having a second input operably coupled to an output of the second differential amplifier.

8. The system of claim 7 , wherein the system comprises a converter operable to convert a plurality of digital outputs to a binary output, each digital output of the plurality of digital outputs being operably coupled to an output from each of the plurality of comparators.

9. The system of claim 1 , wherein the sampling circuit comprises a plurality of comparators, the offset of each comparator of the plurality of comparators is corrected individually using a stored offset value.

10. The system of claim 9 , wherein the stored offset value is determined according to a counter operably coupled to each comparator output.

11. A method for sampling an RF signal, the method comprising:
inputting the RF signal via a plurality of capacitors to produce a plurality of RF inputs;
AC-coupling each reference level of a plurality of reference levels to an RF input of the plurality of RF inputs; and
sampling each AC-coupled reference level to produce a plurality of digital outputs.

12. The method of claim 11 , wherein the method comprises converting the plurality of digital outputs to a binary output.

13. The method of claim 11 , wherein the method comprises producing the plurality of reference levels using a resistors divider chain between a first reference input and a second reference input.

14. The method of claim 13 , wherein the method comprises selectably setting the first reference input and the second reference input to the same voltage during a power-up.

15. The method of claim 11 , wherein sampling comprises operably coupling each AC-coupled reference level to a comparator of a plurality of comparators, the plurality of comparators being controlled by a sample clock.

16. The method of claim 11 , wherein sampling comprises inputting a first AC-coupled reference level and a second AC-coupled reference level to a first comparator and a second comparator, the first AC-coupled reference level being coupled to at least two inputs of the first comparator and being coupled to a first input of the second comparator, the second AC-coupled reference level being coupled to a second input of the second comparator.

17. The method of claim 11 , wherein sampling comprises inputting a first AC-coupled reference level and a second AC-coupled reference level to a first differential amplifier and a second differential amplifier, the first AC-coupled reference level being coupled to at least two inputs of the first differential amplifier and being coupled to a first input of the second differential amplifier, the second AC-coupled reference level being coupled to a second input of the second differential amplifier, wherein the sampling comprises inputting an output of the first differential amplifier and an output of the second differential amplifier to a first comparator and a second comparator, the output of the first differential amplifier being coupled to at least two inputs of the first comparator and being coupled to a first input of the second comparator, the output of the second differential amplifier being coupled to a first input of the second comparator.

18. The method of claim 17 , wherein the method comprises converting a plurality of digital outputs to a binary output, each digital output of the plurality of digital outputs being operably coupled to an output from each of the plurality of comparators.

19. The method of claim 11 , wherein the method comprises setting a comparator offset value for use in sampling.

20. The method of claim 19 , wherein the method comprises determining the comparator offset value according to a counter.

Assignees

• Maxlinear Asia Singapore PTE LTD

Inventors

• Lye William Michael
• Zortea Anthony Eugene
• Chana Jatinder

Classifications

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• H03M1/365

  the voltage divider being a single resistor string · CPC title

• H03M1/1023

  Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03M1/204

  in which one or more virtual intermediate reference signals are generated between adjacent original reference signals, e.g. by connecting pre-amplifier outputs to multiple comparators · CPC title

• H03K5/249

  using clock signals · CPC title