LPS solder paste based low cost fine pitch pop interconnect solutions

Patent metadata

Field	Value
Publication number	US-10586779-B2
Application number	US-201715792569-A
Country	US
Kind code	B2
Filing date	Oct 24, 2017
Priority date	Mar 28, 2014
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400° C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.

First claim

What is claimed is:

1. A method of forming a semiconductor package, comprising:
providing a first substrate having a plurality of first contact pads formed on an interior region of the first substrate and a plurality of second contact pads formed on a peripheral region of the first substrate;
printing a no-slump solder paste onto the first substrate to form a plurality of interconnects having an aspect ratio of 2:1 or greater, wherein each interconnect is printed onto one of the second contact pads, the no-slump solder paste comprising a high melting point material and a delivery vehicle;
attaching a first device die to the first substrate, wherein each of a plurality of first bonding pads on the first device die are electrically coupled to one of the first contact pads with a solder bump; and
curing the no-slump solder paste to entirely surround particles of the high melting point material by an intermetallic shell and to separate the particles of the high melting point material from the delivery vehicle.

2. The method of claim 1 , wherein curing the no-slump solder paste comprises a liquid phase sintering process.

3. The method of claim 2 , wherein the no-slump solder paste comprises copper particles and a SnBi solder.

4. The method of claim 1 , wherein the interconnects are printed to a height of 400 μm or greater.

5. The method of claim 1 , wherein the first device die is attached to the first substrate before the plurality of interconnects have been printed.

6. The method of claim 1 , wherein printing the plurality of interconnects comprises printing a lower portion of the interconnects with a first printing process and printing an upper portion of the interconnects with a second printing process.

7. The method of claim 6 , wherein the lower portion is a no-slump solder paste comprising copper particles, a solder material, and a polymer matrix, and the upper portion is a solder bump.

8. The method of claim 1 , wherein attaching a first device die to the first substrate comprises reflowing the solder bumps, and wherein the reflow temperature is high enough to cure the no-slump solder paste.

9. The method of claim 1 , further comprising:
forming a mold layer over the first substrate; and
forming a plurality of through mold vias through the mold layer in order to expose the second landing pads prior to printing the interconnects.

10. The method of claim 1 , further comprising, attaching a second substrate to top surfaces of the interconnects, wherein a plurality of second bonding pads formed on the second substrate are each electrically coupled to one of the second contact pads by a interconnect.

11. A method of forming a semiconductor package comprising:
providing a first substrate having a plurality of first contact pads formed on an interior region of the first substrate and a plurality of second contact pads formed on a peripheral region of the first substrate;
printing a no-slump solder paste onto the first substrate to form a plurality of interconnects, wherein each interconnect is printed onto one of the second contact pads and wherein the interconnects have an aspect ratio of at least 2:1, the no-slump solder paste comprising a high melting point material and a delivery vehicle;
attaching a first device die to the first substrate, wherein each of a plurality of first bonding pads on the first device die are electrically coupled to one of the first contact pads with a solder bump;
curing the no-slump solder paste with a liquid phase sintering process to entirely surround particles of the high melting point material by an intermetallic shell and to separate the particles of the high melting point material from the delivery vehicle;
attaching a second substrate to top surfaces of the interconnects, wherein a plurality of second bonding pads formed on the second substrate are each electrically coupled to one of the second contact pads on the first substrate by an interconnect; and
attaching a second device die to the second substrate, wherein the second device die is electrically coupled to the second contact pads.

12. The method of claim 11 further comprising:
forming a mold layer over the first substrate; and
forming a plurality of through mold vias through the mold layer in order to expose the second landing pads prior to printing the interconnects.

13. The method of claim 11 , wherein attaching a first device die to the first substrate comprises reflowing the solder bumps, and wherein the reflow temperature is high enough to cure the no-slump solder paste.

Assignees

• Intel Corp

Inventors

• Raravikar Nachiket R
• Matayabas Jr James C
• Mathkar Akshay

Classifications

• B23K35/22

  characterised by the composition or nature of the material · CPC title

• B23K35/025

  Pastes, creams or slurries · CPC title

• B23K35/302

  Cu as the principal constituent · CPC title

• B23K2101/40

  Semiconductor devices · CPC title

• B23K35/262

  Sn as the principal constituent · CPC title