Semiconductor package with programmable signal routing

Patent metadata

Field	Value
Publication number	US-10586764-B2
Application number	US-201616072219-A
Country	US
Kind code	B2
Filing date	Mar 31, 2016
Priority date	Mar 31, 2016
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

Semiconductor packages with programmable routing pathways are disclosed. The semiconductor package may have a source trace that may be electrically coupled to two or more different electrical pathways, where any of the electrical pathways may be activated to provide an electrical connection between the source trace and one or more destination nodes. Each of the electrical pathways may have a corresponding metal well with a correspond airgap overlying the metal well, as well as corresponding heating elements. If a particular heating element is energized, the heating element may melt metal in a corresponding metal well and the molten metal may migrate by capillary action into the overlying airgap to complete an electrical connection between the source trace and a destination node.

First claim

The claimed invention is:

1. A semiconductor package, comprising:
a first build-up layer, the first build-up layer having a source trace;
a second build-up layer overlying the first build-up layer, the second build-up layer having a first metal well and a second metal well, the first metal well and the second metal well electrically coupled to the source trace; and
a third build-up layer overlying the second build-up layer and defining a first gap overlying the first metal well and a second gap overlying the second metal well, the third build-up layer further having a first pad at least partially overlying the first gap and a second pad at least partially overlying the second metal well.

2. The semiconductor package of claim 1 , further comprising a die, wherein a first node of the die is electrically coupled to the first pad and a second node of the die is electrically coupled to the second pad.

3. The semiconductor package of claim 2 , wherein the first node is electrically coupled to the first pad using a die-to-package interconnect, wherein a melting point of the first metal well is less than a melting point of the die-to-package interconnect.

4. The semiconductor package of claim 1 , further comprising a first die and a second die, wherein a first node of the first die is electrically coupled to the first pad and a second node of the second die is electrically coupled to the second pad.

5. The semiconductor package of claim 1 , wherein the second build-up layer further includes a first heating element and a second heating element.

6. The semiconductor package of claim 5 , wherein the first heating element, when energized, is configured to heat the first metal well, wherein heating the first metal well results in melting metal in the first metal well.

7. The semiconductor package of claim 5 , wherein the third build-up layer further includes a third heating element and a fourth heating element, wherein the third heating element, when energized, is configured to heat the first gap, and wherein the fourth heating element, when energized, is configured to heat the second gap.

8. The semiconductor package of claim 1 , wherein the first metal well comprises at least one of: (i) solder paste; (ii) lead-free solder; or (iii) a tin alloy.

9. The semiconductor package of claim 1 , wherein the first metal well and the second metal well are provided in contact with the source trace.

10. The semiconductor package of claim 1 , wherein a sidewall of the first gap includes a metal coating.

11. The semiconductor package of claim 1 , further comprising one or more package-to-board interconnects, wherein a melting point of the first metal well is less than a melting point of the package-to-board interconnect.

12. A method, comprising:
forming a first build-up layer, the first build-up layer having a source trace;
forming a second build-up layer overlying the first build-up layer;
removing a first portion of the second build-up layer and a second portion of the second build-up layer;
filling the first portion with a first metal to form a first metal well and filling the second portion with a second metal to form a second metal well;
forming a third build-up layer overlying the second build-up layer;
forming a first airgap over the first metal well and forming a second airgap over the second metal well; and
forming a first pad over the first airgap and forming a second pad over the second airgap.

13. The method of claim 12 , wherein forming the first build-up layer comprises forming the first build-up layer on a topside of a package core.

14. The method of claim 12 , further comprising attaching a first node of a die to the first pad and a second node of the die to the second pad.

15. The method of claim 14 , wherein the die comprises a die-to-package interconnect, and wherein a melting point of the first metal is greater than a melting point of the die-to-package interconnect.

16. The method of claim 12 , wherein removing the first portion of the second build-up layer further comprises at least one of: (i) laser ablating the first portion; (ii) wet etching the first portion; or (iii) dry etching the first portion.

17. The method of claim 12 , wherein filling the first portion with the first metal to form the first metal well comprises disposing a solder paste in the first portion.

18. The method of claim 12 , wherein forming the first airgap over the first metal well comprises laser ablating the first airgap.

19. The method of claim 12 , wherein forming the first airgap over the first metal well comprises providing metal on a sidewall of the first airgap.

20. The method of claim 12 , wherein forming the second build-up layer further comprises forming a first heating element and a second heating element.

Assignees

• Intel Corp

Inventors

• Aoki Russell S
• Ziakas Dimitrios

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H01L2224/13147

  Electricity · mapped topic

• H01L2224/13111

  Electricity · mapped topic

• H01L2224/16225

  Electricity · mapped topic

• H01L2924/15311

  Electricity · mapped topic