Fabrication method of all solid-state thin-film battery

US10581109B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10581109-B2
Application numberUS-201715474570-A
CountryUS
Kind codeB2
Filing dateMar 30, 2017
Priority dateMar 30, 2017
Publication dateMar 3, 2020
Grant dateMar 3, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of forming an all solid-state thin-film battery that can be scaled down and be integrated into a CMOS process is provided. The method includes a lift-off process in which battery material layers formed upon a patterned sacrificial material are removed from a bottom electrode, while battery material layers that are formed directly on a surface of the bottom electrode remain after performing the lift-off process. In some embodiments, a solid-state lithium based battery can be formed that includes a thin lithiated cathode material layer (thickness of less than 200 nm) composed of LiCoO 2 . Such a solid-state lithium based battery exhibits enhanced battery performance in terms of charge rate and specific charge capacity.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming an all solid-state thin-film battery, the method comprising: forming a patterned sacrificial material directly on a surface of a bottom electrode, wherein the patterned sacrificial material consists of a pre-patterned metallic material that is applied directly to the surface of the bottom electrode by a mechanical force and contains an opening that physically exposes a portion of the surface of the bottom electrode; forming an all solid-state battery stack on an entirety of a sidewall and a topmost surface of the patterned sacrificial material and on the physically exposed portion of the bottom electrode in the opening; and performing a lift-off process to remove the patterned sacrificial material and the all solid-state battery stack formed on the topmost surface of the patterned sacrificial material from the bottom electrode, while maintaining the all solid-state battery stack on the physically exposed portion of the surface of the bottom electrode, wherein the lift-off process comprises releasing the mechanical force. 2. The method of claim 1 , further comprising forming an air and/or moisture impermeable structure on physically exposed surfaces of the bottom electrode and surrounding the all solid-state battery stack that remains on the surface of the bottom electrode. 3. The method of claim 1 , wherein the all solid-state battery stack comprises, from bottom to top, a cathode layer, a solid-state electrolyte layer and a top electrode. 4. The method of claim 3 , wherein the all solid-state battery stack further comprises an anode region located between solid-state electrolyte layer and the top electrode. 5. The method of claim 4 , wherein the all solid-state battery stack further comprises a liner located between the solid-state electrolyte layer and the anode region. 6. The method of claim 3 , wherein the all solid-state battery stack is a solid-state lithium based battery stack, the cathode layer is composed of a lithiated cathode material, and the solid-state electrolyte layer is composed of a lithium-based solid-state electrolyte. 7. The method of claim 6 , wherein the all solid-state battery stack further comprises an anode region located between solid-state electrolyte layer and the top electrode, wherein the anode region comprises a lithium ion generator or lithium intercalation active material. 8. The method of claim 7 , wherein the all solid-state battery stack further comprises a liner located between the solid-state electrolyte layer and the anode region, wherein the liner comprises a nucleation enhancement liner. 9. The method of claim 1 , wherein the bottom electrode is formed on a textured surface of a substrate prior to forming the patterned sacrificial material on the bottom electrode. 10. The method of claim 1 , wherein the bottom electrode is formed on a non-textured surface of a substrate prior to forming the patterned sacrificial material on the bottom electrode. 11. A method of forming an all solid-state thin-film battery, the method comprising: forming a patterned sacrificial material on a surface of a bottom electrode, wherein the patterned sacrificial material consists of pre-patterned metallic material that is applied to the surface of the bottom electrode by an adhesive and contains an opening that physically exposes a portion of the surface of the bottom electrode; forming an all solid-state battery stack on an entirety of a sidewall and a topmost surface of the patterned sacrificial material and on the physically exposed portion of the bottom electrode in the opening; and performing a lift-off process to remove the patterned sacrificial material and the all solid-state battery stack formed on the patterned sacrificial material from the bottom electrode, while maintaining the all solid-state battery stack on the physically exposed portion of the surface of the bottom electrode, wherein the lift-off process comprises peeling the patterned sacrificial material from the adhesive.

Assignees

Inventors

Classifications

  • Solid materials · CPC title

  • Batteries in portable systems, e.g. mobile phone, laptop · CPC title

  • of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy · CPC title

  • Small-sized flat cells or batteries for portable equipment · CPC title

  • inorganic · CPC title

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What does patent US10581109B2 cover?
A method of forming an all solid-state thin-film battery that can be scaled down and be integrated into a CMOS process is provided. The method includes a lift-off process in which battery material layers formed upon a patterned sacrificial material are removed from a bottom electrode, while battery material layers that are formed directly on a surface of the bottom electrode remain after perfor…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01M10/0436. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 03 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).