Self-biasing and self-sequencing of depletion-mode transistors

Patent metadata

Field	Value
Publication number	US-10580892-B2
Application number	US-201816182458-A
Country	US
Kind code	B2
Filing date	Nov 6, 2018
Priority date	Aug 29, 2016
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

A transistor circuit includes a transistor having a gate terminal and first and second conduction terminals, a first circuit configured to convert an AC input signal of the transistor circuit to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor, a second circuit configured to convert the AC input signal of the transistor circuit to a control voltage, and a switching circuit configured to apply a first voltage to the first conduction terminal of the transistor in response to the control voltage.

First claim

What is claimed is:

1. A transistor circuit comprising:
a transistor having a gate terminal and first and second conduction terminals;
a first circuit configured to convert an AC input signal of the transistor circuit to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor, the first circuit comprising an RF coupler, a rectifier, and a voltage regulator;
a second circuit configured to convert the AC input signal of the transistor circuit to a control voltage; and
a switching circuit configured to apply a first voltage to the first conduction terminal of the transistor in response to the control voltage;
wherein the first circuit, the second circuit, and the switching circuit are configured to apply the gate bias voltage to the gate terminal of the transistor before the first voltage is applied to the first conduction terminal of the transistor.

2. The transistor circuit as defined in claim 1 , wherein the transistor comprises a depletion mode transistor.

3. The transistor circuit as defined in claim 2 , wherein the gate bias voltage is negative and the first voltage is positive.

4. The transistor circuit as defined in claim 1 , wherein the rectifier comprises a diode rectifier.

5. The transistor circuit as defined in claim 1 , wherein the rectifier comprises a half bridge rectifier.

6. The transistor circuit as defined in claim 1 , wherein the rectifier comprises a full bridge rectifier.

7. The transistor circuit as defined in claim 1 , wherein the voltage regulator comprises a Zener diode.

8. The transistor circuit as defined in claim 1 , wherein the RF coupler comprises a directional coupler.

9. The transistor circuit as defined in claim 1 , wherein the second circuit comprises an RF coupler and a rectifier.

10. The transistor circuit as defined in claim 1 , wherein the transistor comprises a gallium nitride depletion mode power transistor.

11. The transistor circuit as defined in claim 1 , implemented as a discrete component.

12. The transistor circuit as defined in claim 1 , implemented as a chip-and-wire circuit on a substrate.

13. The transistor circuit as defined in claim 1 , monolithically fabricated on a same die with the transistor.

14. A method for operating a transistor having a gate terminal and first and second conduction terminals, comprising:
converting an AC input signal to a gate bias voltage and applying the gate bias voltage to the gate terminal of the transistor using a first circuit comprising an RF coupler, a rectifier, and a voltage regulator;
converting the AC input signal to a control voltage; and
after applying the gate bias voltage to the gate terminal of the transistor, applying a first voltage to the first conduction terminal of the transistor in response to the control voltage.

15. The method as defined in claim 14 , wherein the transistor comprises a gallium nitride depletion mode power transistor, wherein the gate bias voltage applied to the gate terminal of the transistor is negative and wherein the first voltage applied to the first conduction terminal of the transistor is positive.

16. A transistor circuit comprising:
a depletion mode RF power transistor having a gate terminal, a drain terminal and a source terminal;
a first circuit configured to convert an input RF signal to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor, the first circuit comprising an RF coupler, a rectifier, and a voltage regulator;
a second circuit configured to convert the RF input signal to a control voltage; and
a switching circuit configured to apply a drain voltage to the drain terminal of the transistor in response to the control voltage, wherein the first and second circuits and the switching circuit are configured to apply the gate bias voltage to the gate terminal of the transistor before the drain voltage is applied to the drain terminal of the transistor.

17. The transistor circuit as defined in claim 16 , wherein the gate bias voltage is negative and the drain voltage is positive.

18. The transistor circuit as defined in claim 16 , wherein the second circuit comprises an RF coupler and a rectifier.

19. The transistor circuit as defined in claim 16 , implemented as a discrete component.

20. The transistor circuit as defined in claim 16 , implemented as a chip-and-wire circuit on a substrate.

21. The transistor circuit as defined in claim 16 , monolithically fabricated on a same die with the transistor.

Assignees

• Macom Tech Solutions Holdings Inc

Inventors

• Achiriloaie Benone
• Hokenson Eric

Classifications

• H03F2200/297

  the loading circuit of an amplifying stage comprising a capacitor · CPC title

• H03F2200/99

  A diode as rectifier being used as a detecting circuit in an amplifying circuit · CPC title

• H03F2200/387

  A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier · CPC title

• H03F3/245

  with semiconductor devices only · CPC title

• H03F2200/27

  A biasing circuit node being switched in an amplifier circuit · CPC title