Encoding and decoding variable length instructions

Patent metadata

Field	Value
Publication number	US-10579381-B2
Application number	US-201715821930-A
Country	US
Kind code	B2
Filing date	Nov 24, 2017
Priority date	Nov 23, 2016
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

Methods of encoding and decoding are described which use a variable number of instruction words to encode instructions from an instruction set, such that different instructions within the instruction set may be encoded using different numbers of instruction words. To encode an instruction, the bits within the instruction are re-ordered and formed into instruction words based upon their variance as determined using empirical or simulation data. The bits in the instruction words are compared to corresponding predicted values and some or all of the instruction words that match the predicted values are omitted from the encoded instruction.

First claim

What is claimed is:

1. Decoding hardware comprising:
an input arranged to receive one or more fetched instruction words;
hardware logic configured to determine an encoding type from one or more of the fetched instruction words;
word selection logic configured to generate an ordered sequence of instruction words by selecting, for each of the instruction words in the sequence, either a fetched instruction word or a predicted instruction word, wherein the predicted instruction words are generated using empirical and/or simulation data, and to concatenate the instruction words in the ordered sequence to form an encoded instruction;
re-order hardware logic configured to re-order bits in the encoded instruction according to the encoding type to generate a decoded instruction; and
an output arranged to output the decoded instruction.

2. The decoding hardware according to claim 1 , wherein the word selection logic is further configured to remove one or more control bits from the fetched instruction words prior to generating the ordered sequence of instruction words.

3. The decoding hardware according to claim 1 , wherein the word selection logic is further configured to remove any control bits from the fetched instruction words prior to generating the ordered sequence of instruction words.

4. The decoding hardware according to claim 1 , wherein the one or more fetched instruction words comprises an ordered sequence of fetched instruction words and the word selection logic is configured to generate an ordered sequence of instruction words by selecting, for each of the instruction words in the sequence, either a corresponding fetched instruction word or a corresponding predicted instruction word.

5. The decoding hardware according to claim 4 , wherein each fetched instruction word comprises one or more control bits and wherein the word selection logic is configured to perform the selection of the fetched instruction word or a corresponding predicted instruction word based on values of one or more of the control bits in any prior fetched instruction words in the ordered sequence.

6. The decoding hardware according to claim 1 , wherein the one or more fetched instruction words comprises an ordered sequence of fetched instruction words and the word selection logic is configured to generate an ordered sequence of instruction words by selecting, for each of the instruction words in the sequence, either a next corresponding fetched instruction word or a corresponding predicted instruction word.

7. The decoding hardware according to claim 6 , wherein the word selection logic is configured to perform the selection of either a next fetched instruction word in the ordered sequence of fetched instruction words or a corresponding predicted instruction word based upon a value of a bit in a mask identified based on the encoding type.

8. The decoding hardware according to claim 1 , wherein the re-order hardware logic is configured to re-order bits in the encoded instruction according to the encoding type to generate a decoded instruction by re-ordering bits in the encoded instruction based on mapping data identified based on the encoding type.

9. The decoding hardware according to claim 1 , wherein the hardware logic configured to determine an encoding type is arranged to determine an encoding type from one or more control bits in a first of the fetched instruction words.

10. The decoding hardware according to claim 1 , wherein the encoding type corresponds to a type of ALU on which the instruction will be executed.

11. A method of decoding instructions comprising:
receiving, in a decode stage of a processor, one or more fetched instruction words;
determining an encoding type from one or more of the fetched instruction words;
generating an ordered sequence of instruction words by selecting, for each of the instruction words in the sequence, either a fetched instruction word or a predicted instruction word, wherein the predicted instruction words are generated using empirical and/or simulation data;
concatenating the instruction words in the ordered sequence to form an encoded instruction and re-ordering bits in the encoded instruction according to the encoding type to generate a decoded instruction; and
outputting the decoded instruction.

12. The method according to claim 11 , further comprising:
fetching, in a fetch stage of a processor, one or more instruction words from memory.

13. The method according to claim 12 , wherein the one or more fetched instruction words comprises a pre-defined number of instruction words.

14. The method according to claim 12 , wherein fetching one or more instructions from memory comprises:
fetching one or more control bits from a plurality of instruction words;
determining a number of instruction words to fetch based on the fetched control bits; and
fetching the number of instruction words.

15. A method of encoding instructions from an instruction set, the method comprising:
receiving an instruction from the instruction set;
re-ordering and grouping bits in the received instruction into a plurality of instruction words according to an encoding type to generate an ordered sequence of instruction words;
comparing bit values in one or more of the instruction words in the ordered sequence to their corresponding predicted values and generating a compressed version of the instruction by omitting one or more of the instruction words in the ordered sequence based on the comparison, wherein the predicted values are generated using empirical and/or simulation data; and
outputting the compressed version of the instruction.

16. The method according to claim 15 , wherein the compressed versions of different groups of instructions within the instruction set comprise different numbers of instruction words.

17. The method according to claim 15 , wherein generating a compressed version of the instruction comprises:
omitting one or more instruction words from the ordered sequence that only comprise bits that have values that match the predicted values for those bits;
and optionally wherein, generating a compressed version of the instruction further comprises:
setting one or more bits to indicate which instruction words have been omitted from the ordered sequence.

18. An integrated circuit manufacturing system comprising:
a non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that describes decoding hardware according to claim 1 ;
a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the decoding hardware; and
an integrated circuit generation system configured to manufacture the decoding hardware according to the circuit layout description.

19. A method comprising:
receiving, at an input, mapping data for an instruction set and instruction data describing instructions in an instruction set in canonical form;
parsing the mapping data and instruction data using a grammar library;
generating, in a code and data generation engine, both encoding software and a hardware description of a decoder based on the parsed mapping data and instruction data, wherein the decoder comprises decoding hardware according to claim 1 ; and
outputting the encoding software and the hardware description of a decoder.

20. The method according to claim 19 , further comprising:
generating debugging data and documentation in human-readable

Assignees

• Imagination Tech Ltd

Inventors

• Nield Simon Thomas
• Mccarthy James

Classifications

• G06F9/30149 Primary

  of variable length instructions · CPC title

• G06F9/30178

  of compressed or encrypted instructions · CPC title

• G06F9/30152

  Determining start or end of instruction; determining instruction length · CPC title

• G06F9/30163

  with implied specifier, e.g. top of stack · CPC title

• G06F8/443

  Optimisation · CPC title