Circuit structure and method for high-speed forward error correction
US-9331714-B1 · May 3, 2016 · US
US10574262B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10574262-B2 |
| Application number | US-201816152479-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 5, 2018 |
| Priority date | Jun 30, 2014 |
| Publication date | Feb 25, 2020 |
| Grant date | Feb 25, 2020 |
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Techniques for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer are provided. A PCS transmit structure is configured to receive data from a MAC sublayer, the PCS transmit structure comprising a first FEC hardware module that inserts one or more alignment markers in the data and performs FEC encoding, in a first clock domain, on the one or more alignment markers and the data to generate FEC encoded data. Further, a PCS receive structure configured to receive the FEC encoded data from the PCS transmit structure, the PCS receive structure comprising a second FEC hardware module is configured to perform FEC decoding, in the second clock domain, on the FEC encoded data to generate FEC decoded data, and remove the one or more alignment markers from the FEC decoded data.
Opening claim text (preview).
The claims are as follows: 1. A system comprising: a physical coding sublayer (PCS) transmit structure configured to receive data from a media access control (MAC) sublayer, the PCS transmit structure comprising a first forward error-correction (FEC) hardware module configured to: insert one or more alignment markers in the data; and perform FEC encoding, in a first clock domain, on the one or more alignment markers and the data to generate FEC encoded data; wherein the PCS transmit structure is further configured to transmit the FEC encoded data from the first clock domain with a first clock cycle to a second clock domain with a second clock cycle; and a PCS receive structure configured to receive the FEC encoded data from the PCS transmit structure, the PCS receive structure comprising a second FEC hardware module configured to: perform FEC decoding, in the second clock domain, on the FEC encoded data to generate FEC decoded data; and remove the one or more alignment markers from the FEC decoded data. 2. The system of claim 1 , wherein the first FEC hardware module performs Reed-Solomon encoding on the one or more alignment markers and the data. 3. The system of claim 1 , wherein the second FEC hardware module performs Reed-Solomon decoding on the FEC encoded data. 4. The system of claim 1 , further comprising: one or more physical media attachment (PMA) lanes configured to transmit the FEC encoded data from the PCS transmit structure to the PCS receive structure. 5. The system of claim 1 , further comprising: one or more deskewing queues on the PCS receive structure, the one or more deskewing queues configured to deskew the FEC encoded data before the one or more alignment markers are removed from the FEC decoded data. 6. The system of claim 1 , wherein the first clock domain comprises a media access control (MAC) Interface (MI) clock domain, and wherein the second clock domain comprises a physical medium attachment (PMA) clock domain. 7. The computer program product of claim 6 , further comprising: computer-readable program code configured to perform Reed-Solomon encoding on the one or more alignment markers and the data in the PCS transmit structure. 8. The computer program product of claim 6 , wherein the PCS transmit structure further comprises an encoder configured to encode, in the first clock domain, the data received from the MAC sublayer into PCS blocks before performing FEC encoding on the data; and wherein the PCS receive structure further comprises a decoder configured to decode, in the second clock domain, the FEC decoded data into MAC blocks, wherein the FEC decoded data is received after FEC decoding is performed on the data by the second FEC hardware module. 9. The system of claim 1 , wherein the PCS transmit structure further comprises an encoder configured to encode, in the first clock domain, the data received from the MAC sublayer into PCS blocks before performing FEC encoding on the data; and wherein the PCS receive structure further comprises a decoder configured to decode, in the second clock domain, the FEC decoded data into MAC blocks, wherein the FEC decoded data is received after FEC decoding is performed on the data by the second FEC hardware module. 10. A computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code comprising: computer-readable program code configured to receive data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer; computer-readable program code configured to insert one or more alignment markers in the data in the PCS transmit structure; computer-readable program code configured to perform FEC encoding, in a first clock domain, on the one or more alignment markers and the data in the PCS transmit structure to generate FEC encoded data, wherein the PCS transmit structure is configured to transmit the FEC encoded data from the first clock domain with a first clock cycle to a second clock domain with a second clock cycle; computer-readable program code configured to transmit the FEC encoded data on one or more physical media attachment (PMA) lanes to a PCS receive structure; and computer-readable program code configured to perform FEC decoding, in the second clock domain, on the FEC encoded data in the PCS receive structure to generate FEC decoded data and remove the one or more alignment markers from the FEC decoded data in the PCS receive structure.
Reed-Solomon codes · CPC title
Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes (H03M13/17 takes precedence) · CPC title
Specific encoding aspects, e.g. encoding by means of decoding · CPC title
Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title
using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels {; Baseband coding techniques specific to data transmission systems (spectral shaping H04L25/03828)} · CPC title
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