Frequency management for interference reduction of A/D converters powered by switching power converters

Patent metadata

Field	Value
Publication number	US-10574252-B2
Application number	US-201816233198-A
Country	US
Kind code	B2
Filing date	Dec 27, 2018
Priority date	Dec 30, 2016
Publication date	Feb 25, 2020
Grant date	Feb 25, 2020

Abstract

In at least some embodiments, a system comprises a frequency generator configured to generate a second clock signal having a second frequency using a first clock signal having a first frequency. The second frequency is offset from the first frequency and each of a plurality of harmonic frequencies of the second frequency is offset from a harmonic frequency of the first frequency. The system also includes a power converter configured to produce a power signal that at least partially corresponds to the second frequency. The system further comprises an analog-to-digital converter (ADC) configured to sample and convert analog voltages at the first frequency. The ADC is powered by the power signal.

First claim

What is claimed is:

1. A system, comprising:
a phase-locked loop (PLL) configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency;
a power converter configured to produce a power signal that corresponds at least in part to the second frequency;
a clock transmitter configured to transmit the first clock signal through a first electrical isolation barrier;
a clock receiver configured to receive the first clock signal from the clock transmitter;
an analog-to-digital converter (ADC) configured to receive the first clock signal from the clock receiver and to sample and convert electrical measurements at the first frequency, the ADC powered by the power signal;
a data transmitter configured to receive an output of the ADC and to transmit the output of the ADC via a second electrical isolation barrier; and
a data receiver configured to receive the output of the ADC from the data transmitter and to direct the received output of the ADC toward a device pin,
wherein the second frequency is offset from the first frequency and each of a plurality of harmonic frequencies of the second frequency is offset from at least one harmonic frequency of the first frequency.

2. The system of claim 1 , further comprising a shunt resistor and an amplifier receiving a voltage across the shunt resistor, the electrical measurements comprise the voltage across the shunt resistor.

3. The system of claim 1 , wherein the power converter comprises a laminated transformer that electrically isolates one portion of the power converter from another portion of the power converter.

Assignees

• Texas Instruments Inc

Inventors

• Snoeij Martijn Fridus
• Ivanov Mikhail Valeryevich
• Massolini Roberto Giampiero
• Johnson Brian David

Classifications

• H03M1/0845

  of power supply variations, e.g. ripple · CPC title

• H03L7/23

  with pulse counters or frequency dividers · CPC title

• H03M1/124 Primary

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title

• H03L7/08

  Details of the phase-locked loop · CPC title

• H03M1/0818 Primary

  of clock feed-through · CPC title