Frequency management for interference reduction of A/D converters powered by switching power converters

Patent metadata

Field	Value
Publication number	US-10218374-B2
Application number	US-201615395212-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Dec 30, 2016
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

In at least some embodiments, a system comprises a frequency generator configured to generate a second clock signal having a second frequency using a first clock signal having a first frequency. The second frequency is offset from the first frequency and each of a plurality of harmonic frequencies of the second frequency is offset from a harmonic frequency of the first frequency. The system also includes a power converter configured to produce a power signal that at least partially corresponds to the second frequency. The system further comprises an analog-to-digital converter (ADC) configured to sample and convert analog voltages at the first frequency. The ADC is powered by the power signal.

First claim

What is claimed is:

1. A system, comprising:
a frequency generator configured to generate a second clock signal having a second frequency using a first clock signal having a first frequency, the second frequency offset from the first frequency and each of a plurality of harmonic frequencies of the second frequency offset from a harmonic frequency of the first frequency;
a power converter configured to produce a power signal that at least partially corresponds to the second frequency; and
an analog-to-digital converter (ADC) configured to sample and convert analog voltages at the first frequency, the ADC powered by the power signal;
wherein the system includes a multi-die package, and wherein the frequency generator is formed on a first die of the package, the ADC is formed on a second die of the package, and the power converter is distributed among the first die and a third die, the power converter comprising a transformer to achieve electrical isolation between the first die and the third die.

2. The system of claim 1 , wherein the power signal is at least partially a direct current (DC) signal comprising an alternating current (AC) component, the AC component corresponding to the second frequency.

3. The system of claim 1 , wherein the frequency generator is selected from the group consisting of: a phase-locked loop (PLL), a delay-locked loop (DLL), a frequency-locked loop (FLL), and a frequency divider.

4. The system of claim 1 , further comprising a data transmitter configured to transmit outputs of the ADC via an electrical isolation barrier to a data receiver.

5. The system of claim 1 , wherein the ADC is configured to sample the analog voltages across a shunt resistor.

6. A system, comprising:
a phase-locked loop (PLL) configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency;
a power converter configured to produce a power signal that corresponds at least in part to the second frequency;
a clock transmitter configured to transmit the first clock signal through a first electrical isolation barrier;
a clock receiver configured to receive the first clock signal from the clock transmitter;
an analog-to-digital converter (ADC) configured to receive the first clock signal from the clock receiver and to sample and convert electrical measurements at the first frequency, the ADC powered by the power signal;
a data transmitter configured to receive an output of the ADC and to transmit the output of the ADC via a second electrical isolation barrier; and
a data receiver configured to receive the output of the ADC from the data transmitter and to direct the received output of the ADC toward a device pin,
wherein the second frequency is offset from the first frequency and each of a plurality of harmonic frequencies of the second frequency is offset from at least one harmonic frequency of the first frequency;
wherein the PLL is configured to produce a third clock signal at a third frequency and to provide the third clock signal to the clock transmitter, and wherein the clock transmitter is configured to transmit the first clock signal to the clock receiver at the third frequency.

7. The system of claim 6 , wherein the power signal comprises a direct current (DC) component and an alternating current (AC) component, the AC component corresponding to the second frequency.

8. The system of claim 6 , further comprising a pair of capacitors forming at least a portion of the first isolation barrier and another pair of capacitors forming at least a portion of the second isolation barrier.

Assignees

• Texas Instruments Inc

Inventors

• Snoeij Martijn Fridus
• Ivanov Mikhail Valeryevich
• Massolini Roberto Giampiero
• Johnson Brian David

Classifications

• H03M1/0818 Primary

  of clock feed-through · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03L7/23

  with pulse counters or frequency dividers · CPC title

• H03M1/124 Primary

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title

• H03M1/08

  of noise {(H03M1/0617 takes precedence)} · CPC title