Level shifter with bypass control

Patent metadata

Field	Value
Publication number	US-10574236-B2
Application number	US-201715682327-A
Country	US
Kind code	B2
Filing date	Aug 21, 2017
Priority date	Aug 21, 2017
Publication date	Feb 25, 2020
Grant date	Feb 25, 2020

Abstract

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include level shifting circuitry for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The integrated circuit may include input logic circuitry for receiving multiple input signals and providing an inverted input signal to the level shifting circuitry based on the multiple input signals. The integrated circuit may include bypass switching circuitry for activating and deactivating the level shifting circuitry based on a bypass control signal and at least one of the multiple input signals.

First claim

What is claimed is:

1. An integrated circuit, comprising:
level shifting circuitry for translating an input signal from a first voltage domain to an output signal for a second voltage domain;
input logic circuitry for receiving multiple input signals and providing an inverted input signal to the level shifting circuitry based on the multiple input signals; and
bypass switching circuitry for activating and deactivating the level shifting circuitry based on a bypass control signal and at least one of the multiple input signals.

2. The integrated circuit of claim 1 , wherein the second voltage domain is different than the first voltage domain.

3. The integrated circuit of claim 1 , wherein the first voltage domain is derived from a system-on-a-chip (SOC) logic voltage supply (VDDSOC), and wherein the second voltage domain is derived from a core voltage supply (VDDCE).

4. The integrated circuit of claim 1 , wherein the input logic circuitry comprises a NOR gate that receives the multiple input signals and provides the inverted input signal to the level shifting circuitry based on the multiple input signals.

5. The integrated circuit of claim 1 , wherein the level shifting circuitry comprises a plurality of transistors arranged for translating the input signal from the first voltage domain to the output signal for the second voltage domain.

6. The integrated circuit of claim 5 , wherein the plurality of transistors include P-type metal-oxide-semiconductor (PMOS) transistors and N-type MOS (NMOS) transistors that are arranged for translating the input signal from the first voltage domain to the output signal for the second voltage domain.

7. The integrated circuit of claim 5 , wherein the plurality of transistors include an output control transistor coupled to an output node of the level shifting circuitry, and wherein the output control transistor is activated based on at least one of the multiple input signals.

8. The integrated circuit of claim 1 , wherein the bypass switching circuitry comprises a bypass transistor that is coupled to the level shifting circuitry, and wherein the bypass transistor operates as a switch for activating and deactivating the level shifting circuitry based on the bypass control signal.

9. The integrated circuit of claim 8 , wherein the bypass switching circuitry comprises an auxiliary transistor coupled to the bypass transistor, and wherein the auxiliary transistor is activated based on at least one of the multiple input signals.

10. The integrated circuit of claim 1 , wherein deactivating the level shifting circuitry with the bypass switching circuitry increases speed performance of the integrated circuit by providing a quicker path for the input signal to propagate through the integrated circuit, and wherein deactivating the level shifting circuitry with the bypass switching circuitry reduces timing delay of the integrated circuit by allowing the input signal to bypass the level shifting circuitry.

11. The integrated circuit of claim 1 , wherein activating the level shifting circuitry with the bypass switching circuitry increases timing delay of the integrated circuit by passing the input signal through the level shifting circuitry.

12. The integrated circuit of claim 1 , wherein the integrated circuit is configured for resolving DC path issues when internal nodes are floating by clamping the internal nodes and forcing a specific state.

13. The integrated circuit of claim 1 , wherein the integrated circuit is configured for memory applications that support large range level shifting by reducing delay overhead when level-shifting is not required and by inhibiting potential issues related to DC path during initial power-up and in case of floating inputs.

14. An integrated circuit, comprising:
level shifting circuitry having a plurality of transistors arranged to translate an input signal from a first voltage domain to an output signal for a second voltage domain;
input logic circuitry that receives multiple input signals and provides an inverted input signal to the level shifting circuitry based on the multiple input signals; and
bypass switching circuitry having a bypass transistor and an auxiliary transistor that operate as switches to activate and deactivate the level shifting circuitry based on a bypass control signal and at least one of the multiple input signals.

15. The integrated circuit of claim 14 , wherein the input logic circuitry comprises a NOR gate that receives the multiple input signals and provides the inverted input signal to the level shifting circuitry based on the multiple input signals.

16. The integrated circuit of claim 14 , wherein the level shifting circuitry comprises a plurality of transistors arranged for translating the input signal from the first voltage domain to the output signal for the second voltage domain.

17. The integrated circuit of claim 16 , wherein the plurality of transistors include an output control transistor coupled to an output node of the level shifting circuitry, and wherein the output control transistor is activated based on at least one of the multiple input signals.

18. The integrated circuit of claim 14 , wherein the bypass transistor operates as a switch for activating and deactivating the level shifting circuitry based on the bypass control signal, and wherein the auxiliary transistor is coupled to the bypass transistor, and wherein the auxiliary transistor is activated based on at least one of the multiple input signals.

19. The integrated circuit of claim 14 , wherein the integrated circuit is configured for memory applications that support large range level shifting by reducing delay overhead when level-shifting is not required and by inhibiting potential issues related to DC path during initial power-up and in case of floating inputs, and wherein the integrated circuit is configured for resolving DC path issues when internal nodes are floating by clamping the internal nodes and forcing a specific state.

20. A method for manufacturing an integrated circuit, the method comprising:
fabricating level shifting circuitry having a plurality of transistors arranged for translating an input signal from a first voltage domain to an output signal for a second voltage domain;
fabricating input logic circuitry for receiving multiple input signals and providing an inverted input signal to the level shifting circuitry based on the multiple input signals; and
fabricating bypass switching circuitry having a bypass transistor and an auxiliary transistor that operate as switches for activating and deactivating the level shifting circuitry based on a bypass control signal and at least one of the multiple input signals.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Chen Andy Wangkun
• Cakir Cagla

Classifications

• G11C8/06

  Address interface arrangements, e.g. address buffers · CPC title

• H03K3/02335

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title

• H03K3/356182

  with additional means for controlling the main nodes · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• H03K19/0185 Primary

  using field effect transistors only · CPC title