Low-power wide-range level shifter

Patent metadata

Field	Value
Publication number	US-2016294373-A1
Application number	US-201514676006-A
Country	US
Kind code	A1
Filing date	Apr 1, 2015
Priority date	Apr 1, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A latch-based level-shifter is provided that includes an edge-triggered pulse generator that drives a switch to switch off and isolate a pair of cross-coupled inverters in the level-shifter from ground for a transition period responsive to rising and falling edges in an input signal.

First claim

What is claimed is:

1 . A circuit, comprising:
a latch including a pair of cross-coupled inverters having a virtual ground node, the latch being configured to level-shift a low-voltage-domain input signal into a high-voltage-domain output signal; a switch coupled between the virtual ground node and ground; and an edge-triggered pulse generator configured to pulse the switch off for a transition period responsive to rising edges in the low-voltage-domain input signal and responsive to falling edges in the low-voltage-domain input signal.

2 . The circuit of claim 1 , further comprising:
a first NMOS access transistor coupled to an output node of a first one of the cross-coupled inverters, and a second NMOS access transistor coupled to an output node of a remaining one of the cross-coupled inverters.

3 . The circuit of claim 2 , further comprising:
a first inverter configured to invert the low-voltage-domain input signal into a first inverter output signal, and wherein a gate of the first NMOS access transistor is configured to be driven by the first inverter output signal; and a second inverter configured to invert the first inverter output signal into a second inverter output signal, and wherein a gate of the second NMOS access transistor is configured to be driven by the second inverter output signal.

4 . The circuit of claim 3 , wherein the first inverter and the second inverter both couple to a low-voltage-domain power supply node configured to supply a low supply voltage, and wherein the cross-coupled inverters both couple to a high-voltage-domain power supply node configured to supply a high supply voltage that is greater than the low supply voltage.

5 . The circuit of claim 3 , further comprising a third inverter having an input node coupled to the output node of the second cross-coupled inverter, and wherein the third inverter is configured to invert a voltage for the output node of the second cross-coupled inverter to produce the high-voltage-domain output signal.

6 . The circuit of claim 1 , wherein the edge-triggered pulse generator comprises a logic gate and a delay chain of inverters.

7 . The circuit of claim 6 , wherein the logic gate comprises an XNOR gate.

8 . The circuit of claim 7 , wherein the delay chain of inverters comprises an odd number of inverters configured to provide a delayed inverted signal to an input of the XNOR gate.

9 . The circuit of claim 6 , wherein the switch comprises an NMOS switch transistor having a source coupled to ground and a drain coupled to the virtual ground node for the cross-coupled inverters, and wherein the XNOR gate is configured to drive a gate of the NMOS switch transistor.

10 . The circuit of claim 1 , wherein a first one of the cross-coupled inverters comprises a first PMOS transistor having a source coupled to a high-voltage-domain power supply node and a drain coupled to a first NMOS transistor having a source coupled to the virtual ground node.

11 . The circuit of claim 10 , wherein a remaining second one of the cross-coupled inverters comprises a second PMOS transistor having a source coupled to the high-voltage-domain power supply node and a drain coupled to a second NMOS transistor having a source coupled to the virtual ground node.

12 . A method, comprising:
in a latch-based level-shifter, level-shifting a rising edge of a low-voltage domain input signal transitioning from ground to a low supply voltage to transition a high-voltage domain output signal from ground to a high supply voltage that is greater than the low supply voltage; responsive to the rising edge of the low-voltage domain input signal, isolating a pair of cross-coupled inverters in the latch-based level-shifter from ground for a first transition period; and upon conclusion of the first transition period, re-coupling the pair of cross-coupled inverters to ground.

13 . The method of claim 12 , further comprising:
in the latch-based level-shifter, level-shifting a falling edge of the low-voltage domain input signal transitioning from the low supply voltage to ground to transition the high-voltage domain output signal from the high supply voltage to ground; responsive to the falling edge of the low-voltage domain input signal, isolating the pair of cross-coupled inverters from ground for a second transition period; and upon conclusion of the second transition period, re-coupling the pair of cross-coupled inverters to ground.

14 . The method of claim 13 , wherein a duration of the first transition period equals a duration of the second transition period.

15 . The method of claim 12 , wherein isolating the pair of cross-coupled inverters comprises switching off a switch transistor coupled between the pair of cross-coupled inverters and ground.

16 . The method of claim 15 , wherein switching off the switch transistor comprises switching off an NMOS switch transistor.

17 . A circuit, comprising:
a latch including a pair of cross-coupled inverters, the latch being configured to level-shift a low-voltage-domain input signal into a high-voltage-domain output signal; and means for isolating the pair of cross-coupled inverters from ground for a transition period responsive to a transition of the low-voltage-domain input signal from ground to a low supply voltage and responsive to a transition of the low-voltage-domain input signal from the low supply voltage to ground and for recoupling the pair of cross-coupled inverters to ground upon termination of each transition period.

18 . The circuit of claim 17 , wherein a first one of the cross-coupled inverters comprises a first PMOS transistor having a source coupled to a high-voltage-domain power supply node configured to supply a high supply voltage that is greater than the low supply voltage, the first PMOS transistor having a drain coupled to a first NMOS transistor having a source coupled to the means for isolating.

19 . The circuit of claim 18 , wherein a remaining second one of the cross-coupled inverters comprises a second PMOS transistor having a source coupled to the high-voltage-domain power supply node and a drain coupled to a second NMOS transistor having a source coupled to means for isolating.

20 . The circuit of claim 19 , further comprising:
a first NMOS access transistor coupled to an output node of a first one of the cross-coupled inverters, and a second NMOS access transistor coupled to an output node of a remaining one of the cross-coupled inverters.

Assignees

• Qualcomm Inc

Inventors

• Grubelich Bjorn Erik

Classifications

• H03K3/356104 Primary

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K3/356017

  using additional transistors in the input circuit (H03K3/356104, H03K3/3562 take precedence) · CPC title