Semiconductor device

Patent metadata

Field	Value
Publication number	US-10573604-B2
Application number	US-201816151585-A
Country	US
Kind code	B2
Filing date	Oct 4, 2018
Priority date	Dec 28, 2016
Publication date	Feb 25, 2020
Grant date	Feb 25, 2020

Abstract

A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side. In a Y-direction, each of the first and second semiconductor chips is disposed at a position closer to the first side than to the second side, while the semiconductor chip is disposed at a position closer to the second side than to the first side. Also, in the Y-direction, the resistive component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the third side toward the fourth side, while the semiconductor chip is disposed at a position closer to the third side than to the fourth side.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of terminals including a first terminal coupled to a first potential, a second terminal coupled to a second potential lower than the first potential, and a third terminal coupled to a ground potential;
a plurality of first semiconductor chips each including a first power transistor coupled to the first terminal;
a plurality of second semiconductor chips each including a second power transistor coupled to the second terminal;
a resistive component including a first electrode electrically coupled to the second power transistor, a second electrode opposite to the first electrode, and a resistive element coupled to the first and second electrodes;
a third semiconductor chip including an amplification circuit electrically coupled to the first and second electrodes of the resistive component; and
a sealing body including a first long side extending in a first direction in plan view, a second long side opposite to the first long side in plan view, a first short side extending in a second direction crossing the first direction in plan view, and a second short side opposite to the first short side in plan view and sealing therein the first semiconductor chips, the second semiconductor chips, and the third semiconductor chip,
wherein, in the second direction, each of the first semiconductor chips and the second semiconductor chips is disposed at a position closer to the first long side of the sealing body than to the second long side thereof, while the third semiconductor chip is disposed at a position closer to the second long side of the sealing body than to the first long side thereof,
wherein, in the first direction, the resistive component is disposed at a position closer to the first short side than to the second short side of the sealing body, and
wherein the resistive component is arranged between the first short side of the sealing body and the second semiconductor chips in the first direction.

2. The semiconductor device according to claim 1 ,
wherein the first semiconductor chips are disposed at a position closer to the second short side than to the first short side of the sealing body in the first direction, and
wherein the first semiconductor chips are arranged between the second short side of the sealing body and the second semiconductor chips in the first direction.

3. The semiconductor device according to claim 2 ,
wherein the first semiconductor chips are arranged between the resistive component and the second semiconductor chips in the first direction.

4. The semiconductor device according to claim 3 ,
wherein, in plan view, a wiring substrate is disposed between the third semiconductor chip and the second short side of the sealing body, and
wherein the third semiconductor chip is coupled to a gate electrode of each of the first semiconductor chips via the wiring substrate.

5. A semiconductor device, comprising:
a plurality of first semiconductor chips each including a first surface, a first surface electrode exposed at the first surface, and a first power transistor coupled to the first surface electrode;
a plurality of second semiconductor chips each including a second surface, a second surface electrode exposed at the second surface, and a second power transistor coupled to the first surface electrode;
a first electronic component including a first electrode electrically coupled to the second power transistor, a second electrode opposite to the first electrode, and a resistive element coupled to the first and second electrodes;
a third semiconductor chip including a third surface, a plurality of third surface electrodes exposed at the third surface, and a first circuit electrically coupled to each of the first and second electrodes of the first electronic component via any of the third surface electrodes;
a first chip mounting portion over which the first semiconductor chips are mounted;
a second chip mounting portion over which the second semiconductor chips are mounted;
a third chip mounting portion over which the third semiconductor chip is mounted;
a sealing body having a first long side extending in a first direction in plan view, a second long side opposite to the first long side in plan view, a first short side extending in a second direction crossing the first direction in plan view, and a second short side opposite to the first short side in plan view and sealing therein the first semiconductor chips, the second semiconductor chips, the third semiconductor chip, the first electronic component, the first chip mounting portion, the second chip mounting portion, and the third chip mounting portion; and
a plurality of leads each coupled to any of the first semiconductor chips, the second semiconductor chips, the third semiconductor chip, and the first electronic component and having a portion thereof sealed in the sealing body and the other portion thereof exposed from one of the first and second long sides of the sealing body.

Assignees

• Renesas Electronics Corp

Inventors

• Muto Kuniharu
• Kanda Ryo

Classifications

• H02M7/003 Primary

  Constructional details, e.g. physical layout, assembly, wiring or busbar connections · CPC title

• H02M7/5387

  in a bridge configuration · CPC title

• H02P27/06

  using DC to AC converters or inverters (H02P27/05 takes precedence) · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title