Semiconductor device

Patent metadata

Field	Value
Publication number	US-10128200-B2
Application number	US-201715833289-A
Country	US
Kind code	B2
Filing date	Dec 6, 2017
Priority date	Dec 28, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side. In a Y-direction, each of the first and second semiconductor chips is disposed at a position closer to the first side than to the second side, while the semiconductor chip is disposed at a position closer to the second side than to the first side. Also, in the Y-direction, the resistive component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the third side toward the fourth side, while the semiconductor chip is disposed at a position closer to the third side than to the fourth side.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of first semiconductor chips each including a first surface, a first surface electrode exposed at the first surface, and a first power transistor coupled to the first surface electrode;
a plurality of second semiconductor chips each including a second surface, a second surface electrode exposed at the second surface, and a second power transistor coupled to the first surface electrode;
a first electronic component including a first electrode electrically coupled to the second power transistor, a second electrode opposite to the first electrode, and a resistive element coupled to the first and second electrodes;
a third semiconductor chip including a third surface, a plurality of third surface electrodes exposed at the third surface, and a first circuit electrically coupled to each of the first and second electrodes of the first electronic component via any of the third surface electrodes;
a first chip mounting portion over which the first semiconductor chips are mounted;
a second chip mounting portion over which the second semiconductor chips are mounted;
a third chip mounting portion over which the third semiconductor chip is mounted;
a sealing body having a first long side extending in a first direction in plan view, a second long side opposite to the first long side in plan view, a first short side extending in a second direction crossing the first direction in plan view, and a second short side opposite to the first short side in plan view and sealing therein the first semiconductor chips, the second semiconductor chips, the third semiconductor chip, the first electronic component, the first chip mounting portion, the second chip mounting portion, and the third chip mounting portion; and
a plurality of leads each coupled to any of the first semiconductor chips, the second semiconductor chips, the third semiconductor chip, and the first electronic component and having a portion thereof sealed in the sealing body and the other portion thereof exposed from one of the first and second long sides of the sealing body,
wherein, in the second direction, each of the first semiconductor chips and the second semiconductor chips is disposed at a position closer to the first long side of the sealing body than to the second long side thereof, while the third semiconductor chip is disposed at a position closer to the second long side of the sealing body than to the first long side thereof, and
wherein, in the first direction, the first electronic component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the first short side of the sealing body toward the second short side thereof, while the third semiconductor chip is disposed at a position closer to the first short side than to the second short side.

2. The semiconductor device according to claim 1 ,
wherein the third surface of the third semiconductor chip has a first side extending in the first direction, a second side located opposite to the first side and between the first side and the second long side of the sealing body, a third side extending in the second direction crossing the first direction, and a fourth side located opposite to the third side and between the third side and the second short side of the sealing body,
wherein the first electrode of the first electronic component is electrically coupled to the third semiconductor chip via a first wire coupled to a first measurement electrode which is among the third surface electrodes,
wherein the second electrode of the first electronic component is electrically coupled to the third semiconductor chip via a second wire coupled to a second measurement electrode which is among the third surface electrodes, and
wherein each of the first and second measurement electrodes is disposed at a position over the third surface which is closer to the third side than to the fourth side.

3. The semiconductor device according to claim 2 ,
wherein each of the first and second measurement electrodes is disposed at a position over the third surface which is closer to the first side than to the second side.

4. The semiconductor device according to claim 1 ,
wherein, in plan view, the first electronic component is disposed at a position closer to the first long side than a center line connecting respective middle points of the first and second short sides of the sealing body.

5. The semiconductor device according to claim 4 ,
wherein the first electrode of the first electronic component is electrically coupled to the third semiconductor chip via a first wire coupled to a first measurement electrode which is among the third surface electrodes,
wherein the second electrode of the first electronic component is electrically coupled to the third semiconductor chip via a second wire coupled to a second measurement electrode which is among the third surface electrodes, and
wherein, in a thickness direction orthogonal to a plane including the first and second directions, a thickness of the first electronic component is larger than respective thicknesses of the second semiconductor chips and the third semiconductor chip.

6. The semiconductor device according to claim 1 ,
wherein the third semiconductor chip is electrically coupled to each of the first semiconductor chips and to each of the second semiconductor chips, and
wherein the third semiconductor chip includes a first drive circuit which drives each of the first power transistors of the first semiconductor chips, a second drive circuit which drives each of the second power transistors of the second semiconductor chips, and the first circuit.

7. The semiconductor device according to claim 6 ,
wherein, in plan view, a wiring substrate is disposed between the third semiconductor chip and the second short side of the sealing body, and
wherein the third semiconductor chip is coupled to a gate electrode of each of the first semiconductor chips via the wiring substrate.

8. The semiconductor device according to claim 1 ,
wherein the first electrode of the first electronic component is mounted over a first component mounting portion via a conductive bonding material,
wherein the second electrode of the first electronic component is mounted over a second component mounting portion spaced apart from the first component mounting portion via the conductive bonding material,
wherein, to the first component mounting portion, a first inner lead extending along a third direction crossing the first direction is coupled,
wherein, to the second component mounting portion, a second inner lead extending along the third direction is coupled,
wherein the first electrode of the first electronic component is electrically coupled to the third semiconductor chip via each of the first inner lead and a first wire coupled to a first measurement electrode which is among the of third surface electrodes, and
wherein the second electrode of the first electronic component is electrically coupled to the third semiconductor chip via each of the second inner lead and a second wire coupled to a second measurement electrode which is among the third surface electrodes.

9. The semiconductor device according to claim 8 ,
wherein the second component mounting portion is coupled to a first outer lead which is among the leads and exposed from the first long side of the sealing body, and
wherein a ground potential is supplied to the first outer lead.

10. The semiconductor device according to claim 9 ,
wherein the first chip mounting portion is coupled to a second outer lead which is among the leads and exposed from the first long side of the sealing body,
whe

Assignees

• Renesas Electronics Corp

Inventors

• Muto Kuniharu
• Kanda Ryo

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title