Modulators

Patent metadata

Field	Value
Publication number	US-10566992-B2
Application number	US-201916375868-A
Country	US
Kind code	B2
Filing date	Apr 5, 2019
Priority date	Aug 31, 2017
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (SPWM) where the pulse-width modulated signal is synchronised to a first clock signal (CLK1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (SPWM) at a first node (304) based on the input signal (SIN) and a feedback signal (SFB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (701) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronised to the first clock signal (CLK1).

First claim

The invention claimed is:

1. A time-encoding modulator circuit comprising:
a hysteretic comparator module configured to generate a time encoded signal at a first node based on an input; and
a hysteresis controller configured to controllably vary, in use in a first mode of operation, an amount of hysteresis applied by the hysteretic comparator module so as to control a cycle period of the time encoded signal within a first defined range;
wherein the hysteretic comparator module is configured such that any change in state of the time encoded signal at the first node is synchronised to a first clock signal.

2. The time-encoding modulator circuit as claimed in claim 1 wherein the hysteresis controller is further configured to control the hysteresis applied by the hysteretic comparator to dither the cycle period of the time encoded signal within said defined range.

3. The time-encoding modulator circuit as claimed in claim 1 wherein hysteresis controller is further operable in a second mode of operation to control the amount of hysteresis applied by the hysteretic comparator to provide a limit cycle frequency which is different to a limit cycle frequency of the first mode.

4. The time-encoding modulator circuit as claimed in claim 1 comprising a counter configured to receive the time encoded signal and generate count values of the number of clock periods of a second clock signal during periods defined by the time encoded signal, wherein the second clock signal is synchronised to the first clock signal.

5. The time-encoding modulator circuit as claimed in claim 4 wherein the hysteresis controller is configured to receive a count value from said counter and to control hysteresis applied by the hysteretic comparator based on said count value.

6. The time-encoding modulator circuit as claimed in claim 4 wherein the time encoded signal comprises cycles of pulses of first and second states and the counter is configured to generate a first count value for the duration of the pulse of the first state of the time-encoded signal during each cycle and a second count value for the duration of the pulse of the second state of the time-encoded signal during each cycle.

7. The time-encoding modulator circuit as claimed in claim 4 wherein second clock signal is the same as the first clock signal.

8. The time-encoding modulator circuit as claimed in claim 4 further comprising a demodulator configured to receive the count values from the counter and generate a digital output signal.

9. The time-encoding modulator circuit as claimed in claim 8 wherein the hysteresis controller is configured to receive said digital output signal to control hysteresis applied by the hysteretic comparator based on said digital output signal.

10. The time-encoding modulator circuit as claimed in claim 8 wherein the demodulator comprises a demodulator input for receiving a first received value, an adder for adding the first received value to an output from a modulus block, a memory for storing the output of the adder and a demodulator comparator for comparing a value stored in the memory to a second received value, wherein the modulus block is configured to apply a modulo operation to the output of the memory based on the second received value and wherein the first and second values are derived from count values received from said counter.

11. The time-encoding modulator circuit as claimed in claim 8 comprising a filter arrangement configured to filter the count values provided to the demodulator.

12. The time-encoding modulator circuit as claimed in claim 1 wherein the circuit is configured such that a feedback signal from the first node is combined with the input signal to generate a combined signal, a loop filter is configured to apply filtering to said combined signal and one input of the hysteretic comparator module is configured to receive an output of the loop filter.

13. The time-encoding modulator circuit as claimed in claim 12 wherein said loop filter is an integrator.

14. The time-encoding modulator circuit as claimed in claim 1 comprising a loop filter configured to receive a feedback signal from the first node and generate a filtered feedback signal and wherein a first input of the hysteretic comparator module receives the input signal and a second input of the hysteretic comparator module receives the filtered feedback signal.

15. The time-encoding modulator circuit as claimed in claim 14 wherein the loop filter comprises a resistor-capacitor filter.

16. The time-encoding modulator circuit as claimed in claim 1 wherein the hysteretic comparator module comprises a latched comparator configured to receive the first clock signal, wherein any changes in output state of the latched comparator is synchronised to the first clock signal.

17. The time-encoding modulator circuit as claimed in claim 1 wherein the hysteretic comparator module comprises a hysteretic comparator and a latch coupled to an output of the hysteretic comparator, wherein the latch is configured to be clocked by the first clock signal.

18. An electronic device comprising the time-encoding modulator circuit of claim 1 .

19. A time-encoding modulator comprising:
a feedforward path for receiving an input signal and outputting a time encoded signal, the feedforward path comprising a loop filter upstream of a hysteretic comparator module;
a feedback path for providing a feedback signal from an output of the hysteretic comparator module to be combined with the input signal, and
a hysteresis controller configured to controllably vary, in use, an amount of hysteresis applied by the hysteretic comparator module so as to control a cycle period of the time encoded signal;
wherein the loop filter is configured to apply filtering to the combined input and feedback signals and the hysteretic comparator module is configured to receive the output of the loop filter and to generate the time encoded signal at the output of the hysteretic comparator module output; and
wherein the hysteretic comparator module is configured such that any change in state of the time encoded signal at the hysteretic comparator module output is synchronised to a first clock signal.

20. A time-encoding modulator for receiving an input signal and outputting a time encoded signal comprising:
a hysteretic comparator module configured to receive the input signal at a first input and a feedback signal at a second input and to generate a time encoded signal at an output node;
a hysteresis controller configured to controllably vary, in use, an amount of hysteresis applied by the hysteretic comparator module so as to control a cycle period of the time encoded signal;
a feedback path coupled to the output node to provide the feedback signal to the second comparator input, and
a loop filter configured to apply filtering to the feedback path;
wherein the hysteretic comparator module is configured such that any change in state of the time encoded signal at the hysteretic comparator module output is synchronised to a first clock signal.

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Lesso John Paul

Classifications

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H03M3/39 Primary

  Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators (of digital delta-sigma modulators H03M7/3004) · CPC title

• H03M1/50 Primary

  with intermediate conversion to time interval (H03M1/64 takes precedence) · CPC title

• H03M3/456

  the modulator having a first order loop filter in the feedforward path · CPC title

• H03M1/508

  the pulse width modulator being of the self-oscillating type · CPC title