Correction technique for analog pulse processing time encoder

Patent metadata

Field	Value
Publication number	US-9705519-B1
Application number	US-201615196496-A
Country	US
Kind code	B1
Filing date	Jun 29, 2016
Priority date	Jun 29, 2016
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A circuit for correcting time encoder errors including a time encoder having a time encoder input, a time encoder output, and a current summing point, and a pulse width modifier coupled to the time encoder output, the pulse width modifier having a current output coupled to the current summing point, and having a corrected output. The pulse width modifier is configured to calibrate duty cycle errors and nonlinearity errors on the time encoder output, to correct the duty cycle errors and the nonlinearity errors on the time encoder output, and to output the corrected output.

First claim

What is claimed is:

1. A circuit for correcting time encoder errors comprising:
a time encoder having a time encoder input, a time encoder output, and a current summing point; and
a pulse width modifier coupled to the time encoder output, the pulse width modifier having a current output coupled to the current summing point, and having a corrected output;
wherein the pulse width modifier is configured to calibrate duty cycle errors and nonlinearity errors on the time encoder output, to correct the duty cycle errors and the nonlinearity errors on the time encoder output, and to output the corrected output.

2. The circuit of claim 1 further comprising:
a first switch between the time encoder input and the current summing point;
a current bank configured to inject selected DC currents into the current summing point; and
a second switch between the current bank and the current summing point;
wherein when the first switch is open and the second switch is closed to connect the current bank to the current summing point and selected DC currents are injected into the current summing point, the pulse width modifier is configured to calibrate and store nonlinearity errors;
wherein when the first switch is open or the time encoder input has a non-time varying input, and the second switch is open, the pulse width modifier is configured to calibrate and store duty cycle errors; and
wherein when the first switch is closed to coupled the time encoder input to the current summing point and the second switch is open, the pulse width modifier is configured to use the stored nonlinearity errors to inject a pre-distortion current via the current output into the current summing point to correct nonlinearity errors on the time encoder output, to use the stored duty cycle errors to correct duty cycle errors on the time encoder output, and to output the corrected output.

3. The circuit of claim 1 wherein the time encoder is a first order time encoder or a higher order time encoder.

4. The circuit of claim 1 wherein the time encoder comprises:
a current source coupled to the current summing point;
an integrator coupled to the current summing point;
a hysteresis quantizer having an input coupled to the current summing point, wherein an output of the hysteresis quantizer is the time encoder output; and
a 1-bit digital to analog converter coupled between the time encoder output and the current summing point.

5. The circuit of claim 4 further comprising:
a transconductance amplifier coupled between the time encoder input and the current summing point.

6. The circuit of claim 4 wherein the integrator comprises a capacitor.

7. The circuit of claim 1 wherein the time encoder comprises:
a first current source coupled to the current summing point;
an first integrator coupled to the current summing point;
a transconductance amplifier coupled to the current summing point, and having an output coupled to a second current summing point;
a second current source coupled to the second current summing point;
a second integrator coupled to the second current summing point;
a hysteresis quantizer coupled to the second current summing point, wherein an output of the hysteresis quantizer is the time encoder output;
a first 1-bit digital to analog converter coupled between the time encoder output and the current summing point; and
a second 1-bit digital to analog converter coupled between the time encoder output and the second current summing point.

8. The circuit of claim 7 wherein:
the first integrator comprises a first capacitor; and
the second integrator comprises a second capacitor.

9. The circuit of claim 1 wherein the pulse width modifier comprises:
a duty cycle corrector coupled to the time encoder output for characterizing duty cycle errors comprising:
a first processor; and
a first memory;

a pulse adjustor coupled to the time encoder output and to the duty cycle corrector for correcting duty cycle errors and for generating the corrected output;
a nonlinearity estimator coupled to the time encoder output for characterizing nonlinearity errors comprising:
a counter configured to count edges on the time encoder output within a period of time;
a second processor; and
a second memory; and

a pre-distortion circuit coupled to the non-linearity estimator and to the current summing point for correcting nonlinearity errors.

10. The circuit of claim 9 wherein:
the first and second processor are one and the same processor.

11. A method for correcting time encoder errors comprising:
providing a time encoder having a time encoder input, a time encoder output, and a current summing point;
providing a pulse width modifier coupled to the time encoder output, the pulse width modifier having a current output coupled to the current summing point, and having a corrected output;
calibrating duty cycle errors on the time encoder output using the pulse width modifier and storing the duty cycle errors;
calibrating nonlinearity errors on the time encoder output using the pulse width modifier and storing the nonlinearity errors;
correcting the duty cycle errors and nonlinearity errors; and
outputting the corrected output.

12. The method of claim 11 further comprising:
disconnecting the time encoder input from the current summing switching point, injecting selected DC currents into the current summing point, and calibrating and storing nonlinearity errors;
disconnecting the time encoder input or providing a non-time varying input on the time encoder input, and calibrating and storing duty cycle errors.

13. The method of claim 11 further comprising
connecting the time encoder input to the current summing switching point;
using the stored nonlinearity errors to inject a pre-distortion current via the current output into the current summing point to correct nonlinearity errors on the time encoder output;
using the stored duty cycle errors to correct duty cycle errors on the time encoder output; and
outputting the corrected output.

14. The method of claim 11 wherein the time encoder is a first order time encoder or a higher order time encoder.

15. The method of claim 11 wherein the time encoder comprises:
a current source coupled to the current summing point;
an integrator coupled to the current summing point;
a hysteresis quantizer having an input coupled to the current summing point, wherein an output of the hysteresis quantizer is the time encoder output; and
a 1-bit digital to analog converter coupled between the time encoder output and the current summing point.

16. The method of claim 11 wherein the time encoder comprises:
a first current source coupled to the current summing point;
an first integrator coupled to the current summing point;
a transconductance amplifier coupled to the current summing point, and having an output coupled to a second current summing point;
a second current source coupled to the second current summing point;
a second integrator coupled to the second current summing point;
a hysteresis quantizer coupled to the second current summing point, wherein an output of the hysteresis quantizer is the time encoder output;
a first 1-bit digital to analog converter coupled between the time encoder output and the current summing point; and
a second 1-bit digital to analog converter coupled between the time encoder output and the second current summing point.

17. The method of claim 11 wherein the pulse width modifier comprises:
a duty cycle corrector coupled to the time encoder output for characterizing duty cyc

Assignees

• Hrl Lab Llc

Inventors

• Baringer Cynthia D

Classifications

• H03M1/06 Primary

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) · CPC title

• H03M7/3073 Primary

  Time · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H03K5/00

  Manipulating of pulses not covered by one of the other main groups of this subclass (circuits with regenerative action H03K3/00, H03K4/00; by the use of non-linear magnetic or dielectric devices H03K3/45) · CPC title