Semiconductor devices

Patent metadata

Field	Value
Publication number	US-10566332-B2
Application number	US-201816192097-A
Country	US
Kind code	B2
Filing date	Nov 15, 2018
Priority date	May 11, 2016
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

First claim

What is claimed is:

1. A semiconductor device, comprising:
active areas and a trench isolation region between the active areas, each of the active areas comprising a longer side extending in a first direction;
buried word lines extending in a second direction, two of the buried word lines intersecting with each of the active areas and separating each of the active areas into a digit line contact area and two cell contact areas, wherein the second direction is not perpendicular to the first direction;
a digit line contact adjacent to the digit line contact area;
a storage node contact adjacent to each of the two cell contact areas, wherein the digit line contact and the storage node contact are substantially coplanar; and
at least one digit line extending in a third direction, wherein the at least one digit line is adjacent to the digit line contact.

2. The semiconductor device of claim 1 , wherein each of the digit line contact and the storage node contact comprises polysilicon.

3. The semiconductor device of claim 1 , wherein each of the digit line contact and the storage node contact comprises polysilicon and a metal.

4. The semiconductor device of claim 1 , wherein the digit line contact comprises a digit line contact plug and a metal plug.

5. The semiconductor device of claim 4 , wherein the digit line contact plug substantially completely covers the digit line contact area.

6. The semiconductor device of claim 1 , wherein the storage node contact comprises a cell contact plug and a metal plug.

7. The semiconductor device of claim 6 , wherein the cell contact plug substantially completely covers the cell contact area.

8. The semiconductor device of claim 1 , further comprising a capacitor electrically connected with the cell contact area.

9. A semiconductor device, comprising:
active areas and a trench isolation region between the active areas, each of the active areas comprising a longer side extending in a first direction;
buried word lines extending in a second direction, two of the buried word lines intersecting with each of the active areas and separating each of the active areas into a digit line contact area and two cell contact areas, wherein the second direction is not perpendicular to the first direction;
a digit line contact adjacent to the digit line contact area;
a storage node contact adjacent to a top surface and a sidewall of each of the two cell contact areas; and
at least one digit line extending in a third direction perpendicular to the second direction, wherein the at least one digit line is adjacent to the digit line contact.

10. The semiconductor device of claim 9 , wherein sidewalls of the storage node contact are aligned with sidewalls of cell contact plugs.

11. The semiconductor device of claim 10 , wherein the cell contact plugs directly contact sidewalls of the active areas.

12. The semiconductor device of claim 9 , wherein sidewalls of the digit line contact are aligned with sidewalls of digit line contact plugs.

13. The semiconductor device of claim 9 , wherein the cell contact areas are located at distal ends of the active areas.

14. The semiconductor device of claim 9 , wherein the digit line contact area is located between two of the buried word lines.

15. The semiconductor device of claim 9 , wherein a top surface of the trench isolation region is recessed relative to a top surface of the active areas.

16. A semiconductor device, comprising:
active areas and a trench isolation region between the active areas, each of the active areas comprising a longer side extending in a first direction;
buried word lines extending in a second direction, two of the buried word lines intersecting with each of the active areas and separating each of the active areas into a digit line contact area and two cell contact areas, wherein the second direction is not perpendicular to the first direction;
a digit line contact on the digit line contact area;
a storage node contact adjacent to a top surface of each of the two cell contact areas and the trench isolation region; and
at least one digit line extending in a third direction, wherein the at least one digit line is adjacent to the digit line contact and the third direction is perpendicular to the second direction.

17. The semiconductor device of claim 16 , wherein a top surface of the trench isolation region is substantially coplanar with a top surface of the active areas.

18. The semiconductor device of claim 16 , wherein a top surface of the trench isolation region is recessed relative to a top surface of the active areas.

19. The semiconductor device of claim 16 , further comprising an insulating material over a conductive material within the active areas, a top surface of the insulating material coplanar with a top surface of an annular spacer surrounding the insulating material.

20. The semiconductor device of claim 16 , further comprising an insulating material over the trench isolation region, a top surface of the insulating material coplanar with a top surface of an annular spacer surrounding the insulating material.

Assignees

• Micron Technology Inc

Inventors

• Wang Kuo-Chen
• Kuan Shih-Fan
• Heineck Lars
• Tang Sanh D

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title