SMD package with top side cooling

US10566260B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10566260-B2
Application numberUS-201816124336-A
CountryUS
Kind codeB2
Filing dateSep 7, 2018
Priority dateSep 8, 2017
Publication dateFeb 18, 2020
Grant dateFeb 18, 2020

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; a top layer arranged at the package top side and electrically connected with the second load terminal; and a heat spreader arranged external of the package body and in electrical contact with the top layer. A top surface of the heat spreader has an area greater than the area of the bottom surface.

First claim

Opening claim text (preview).

What is claimed is: 1. A package enclosing a power semiconductor die, the package having a package body with a package top side, a package footprint side and package sidewalls, the package sidewalls extending from the package footprint side to the package top side, wherein the die has a first load terminal and a second load terminal and is configured to block a blocking voltage applied between said load terminals, wherein the package comprises: a lead frame structure configured to electrically and mechanically couple the package to a support with the package footprint side facing to the support, the lead frame structure comprising at least one first outside terminal extending out of one of the package sidewalls and electrically connected with the first load terminal of the die; a top layer arranged at the package top side and being electrically connected with the second load terminal of the die; and a heat spreader arranged external of the package body and in electrical contact with the top layer, with a bottom surface of the heat spreader facing to the top layer, wherein the heat spreader further has a top surface, an area of the top surface being greater than an area of the bottom surface, wherein the package body is made of a molding mass, wherein the molding mass spatially confines the top layer at the package top side. 2. The package of claim 1 , wherein the area of the heat spreader top surface is at least 120% of the area of the heat spreader bottom surface. 3. The package of claim 1 , wherein a bottom surface of the top layer has a surface area at least 50% and less than 100% of a total surface area of the package top side. 4. The package of claim 1 , wherein the area of the heat spreader bottom surface is within a range of 80% to 100% of a surface area of a top surface of the top layer. 5. The package of claim 1 , wherein a contour of the heat spreader bottom surface matches a contour of the top layer. 6. The package of claim 1 , wherein the area of the heat spreader top surface is within a range of 80% to 120% of a footprint area of the package. 7. The package of claim 1 , wherein the heat spreader comprises sidewalls extending from the bottom surface to the top surface, and wherein at least one of the sidewalls exhibits a profile with one or more non-vertical sections. 8. The package of claim 1 , wherein each of the package footprint side, the package top side, the top layer, the heat spreader bottom surface and the heat spreader top surface is arranged substantially horizontal. 9. The package of claim 1 , wherein the top layer is arranged substantially coplanar with the package top side. 10. The package of claim 1 , wherein the heat spreader is monolithic. 11. The package of claim 1 , wherein the heat spreader is made of an electrically conductive material. 12. The package of claim 1 , wherein the heat spreader is soldered to the top layer. 13. The package of claim 1 , wherein the heat spreader is positively locked to the top layer. 14. The package of claim 1 , further comprising an electrically conductive interconnect layer arranged between and in contact with each of the heat spreader and the top layer. 15. The package of claim 1 , wherein the heat spreader top surface is configured to be coupled to an isolation layer that, and wherein the isolation layer has an area at least 120% of the area of the top layer. 16. The package of claim 1 , wherein the package is a top side cooling package with the top layer being configured for top side cooling. 17. The package of claim 1 , wherein: each of the package top side and the package footprint side extend substantially horizontally; the package sidewalls extend substantially vertically; and a maximum horizontal extension of the package footprint side is at least twice of a maximum vertical extension of the package sidewalls. 18. The package of claim 1 , wherein a blocking voltage of the power semiconductor die is at least 50 V and/or wherein the power semiconductor die includes a monolithic bidirectionally blocking and conducting power semiconductor switch. 19. The package of claim 1 , wherein the package is a surface-mount device (SMD) package.

Assignees

Inventors

Classifications

  • the semiconductor body being completely enclosed · CPC title

  • being the outer leads · CPC title

  • Manufacture or treatment · CPC title

  • Shapes or dispositions · CPC title

  • in encapsulations · CPC title

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Frequently asked questions

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What does patent US10566260B2 cover?
A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including…
Who is the assignee on this patent?
Infineon Technologies Austria Ag
What technology area does this patent fall under?
Primary CPC classification H10W40/22. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 18 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).