Capacitors, integrated assemblies including capacitors, and methods of forming integrated assemblies

Patent metadata

Field	Value
Publication number	US-10566136-B2
Application number	US-201916368601-A
Country	US
Kind code	B2
Filing date	Mar 28, 2019
Priority date	Nov 16, 2017
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container portion has an inner surface and an outer surface. Dielectric material lines the inner and outer surfaces of the upper container portion, and lines the outer surface of the lower pillar portion. A second electrode extends along the inner and outer surfaces of the upper container portion, and along the outer surface of the lower pillar portion. The second electrode is spaced from the first electrode by the dielectric material. Some embodiments include assemblies (e.g., memory arrays) which have capacitors. Some embodiments include methods of forming capacitors.

First claim

We claim:

1. A method of forming an assembly, comprising:
forming a stack comprising a first sacrificial material over a second sacrificial material, and comprising a lattice layer between the first and second sacrificial materials;
forming a pair of neighboring first openings extending through the first and second sacrificial materials, and through the lattice layer;
forming conductive liners along inner surfaces of the neighboring first openings to narrow the neighboring first openings; the conductive liner within one of the neighboring first openings being a first conductive liner, and the conductive liner within the other of the neighboring first openings being a second conductive liner;
forming conductive fill material within the narrowed neighboring first openings to fill the narrowed neighboring first openings; the conductive fill material within said one of the neighboring first openings, together with the first conductive liner, forming a first conductive structure; and the conductive fill material within said other of the neighboring first openings, together with the second conductive liner, forming a second conductive structure;
forming a second opening to partially overlap the first and second conductive structures; the second opening extending to the conductive fill material of the first and second conductive structures, and extending to the first sacrificial material;
removing the first sacrificial material to expose a region of the lattice layer between the first and second conductive structures;
removing the exposed region of the lattice layer, and then removing the second sacrificial material;
removing a portion of the conductive fill material from each of the first and second conductive structures to form the first and second conductive structures into first and second bottom electrodes, respectively; the first bottom electrode having a first lower pillar region comprising a first remaining portion of the conductive fill material laterally surrounded by a lower region of the first conductive liner, and having a first upper container region over the first lower pillar region and comprising an upper region of the first conductive liner; the second bottom electrode having a second lower pillar region comprising a second remaining portion of the conductive fill material laterally surrounded by a lower region of the second conductive liner, and having a second upper container region over the second lower pillar region and comprising an upper region of the second conductive liner;
forming dielectric material along the first and second bottom electrodes; and
forming a common upper electrode along the dielectric material and spaced from the first and second bottom electrodes by the dielectric material.

2. The method of claim 1 , where the forming of the neighboring first openings creates a first inset region extending to under the lattice layer within said one of the neighboring first openings, and creates a second inset region extending to under the lattice layer within said other of the neighboring first openings; where the first conductive liner has a first step extending along the first inset region; and where the second conductive liner has a second step extending along the second inset region.

3. The method of claim 1 , where the lattice layer comprises silicon nitride.

4. The method of claim 1 , where the first sacrificial material comprises silicon dioxide and the second sacrificial material comprises borophosphosilicate glass.

5. The method of claim 1 , where the first sacrificial material comprises amorphous silicon and the second sacrificial material comprises borophosphosilicate glass.

6. The method of claim 1 , comprising forming a conductive interconnect electrically coupled with the common second electrode.

7. The method of claim 6 , where the conductive interconnect includes conductively-doped semiconductor material directly against the common second electrode, and includes metal-containing material directly against the conductively-doped semiconductor material.

8. The method of claim 7 , where the conductively-doped semiconductor material comprises conductively-doped silicon, and where the metal-containing material comprises tungsten.

Assignees

• Micron Technology Inc

Inventors

• Wang Kuo-Chen
• Amaike Hiroshi
• Hattori Kota

Classifications

• H01G4/012

  Form of non-self-supporting electrodes · CPC title

• H01G4/33 Primary

  Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)} · CPC title

• H01G4/40

  Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations · CPC title

• H01G4/018

  Dielectrics · CPC title

• H01G4/005 Primary

  Electrodes · CPC title