Semiconductor device structure with capacitor and method for forming the same

Patent metadata

Field	Value
Publication number	US-9997520-B2
Application number	US-201514815419-A
Country	US
Kind code	B2
Filing date	Jul 31, 2015
Priority date	Jul 31, 2015
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive structure in or over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the conductive structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer. The second dielectric layer has a second opening connected to the first opening and exposing the conductive structure. The semiconductor device structure includes a capacitor covering a first inner wall of the first opening, a second inner wall of the second opening, and a top surface of the conductive structure. The capacitor is electrically connected to the conductive structure.

First claim

What is claimed is:

1. A semiconductor device structure, comprising:
a substrate;
a conductive structure in or over the substrate;
a first dielectric layer over the substrate, wherein the first dielectric layer has a first opening exposing the conductive structure;
a second dielectric layer over the first dielectric layer, wherein the second dielectric layer has a second opening connected to the first opening and exposing the conductive structure, the second dielectric layer has a bottom surface, a first portion of the bottom surface is located directly above the first opening, and the first dielectric layer and the second dielectric layer are made of a same material; and
a capacitor covering a first inner wall of the first opening, a second inner wall of the second opening, and a top surface of the conductive structure, wherein the capacitor is electrically connected to the conductive structure, the first inner wall of the first opening starts at a top of the first dielectric layer, ends at a bottom of the first dielectric layer, and is a first slanted sidewall, the second inner wall of the second opening starts at a top of the second dielectric layer, ends at a bottom of the second dielectric layer, and is a second slanted sidewall, the first portion of the bottom surface is directly connected to the first slanted sidewall and the second slanted sidewall, and the first portion of the bottom surface, the first slanted sidewall, and the second slanted sidewall together form a sawtooth surface.

2. The semiconductor device structure as claimed in claim 1 , wherein a first portion of the capacitor covering the first inner wall, the second inner wall, and the first portion of the bottom surface is in a sawtooth shape.

3. The semiconductor device structure as claimed in claim 1 , wherein the capacitor has a recess in the first opening and the second opening.

4. The semiconductor device structure as claimed in claim 3 , further comprising:
a conductive layer filled in the recess and electrically connected to the capacitor.

5. The semiconductor device structure as claimed in claim 3 , wherein the recess has an upper portion, a lower portion, and a neck portion between the upper portion and the lower portion, and the neck portion has a first width less than a second width of the upper portion and a third width of the lower portion.

6. The semiconductor device structure as claimed in claim 1 , wherein the capacitor has a first electrode layer, a third dielectric layer, and a second electrode layer, the third dielectric layer is between the first electrode layer and the second electrode layer, and the first electrode layer surrounds the third dielectric layer and the second electrode layer.

7. The semiconductor device structure as claimed in claim 6 , wherein a first portion of the first electrode layer covering the first inner wall, the second inner wall, and the first portion of the bottom surface is in a sawtooth shape.

8. A semiconductor device structure, comprising:
a substrate;
a conductive structure in or over the substrate;
a first dielectric layer over the substrate, wherein the first dielectric layer has a first opening exposing the conductive structure, and the first opening continuously shrinks in a direction toward the substrate;
a second dielectric layer over the first dielectric layer, wherein the second dielectric layer has a second opening connected to the first opening and exposing the conductive structure, and a first maximum width of the second opening is greater than a second maximum width of the first opening, the second dielectric layer has a bottom surface, a portion of the bottom surface is located directly above the first opening, and the first dielectric layer and the second dielectric layer are made of a same material; and
a capacitor covering a first inner wall of the first opening, a second inner wall of the second opening, and a top surface of the conductive structure, wherein the capacitor is electrically connected to the conductive structure, the first inner wall of the first opening starts at a top of the first dielectric layer, ends at a bottom of the first dielectric layer, and is a first slanted sidewall, the second inner wall of the second opening starts at a top of the second dielectric layer, ends at a bottom of the second dielectric layer, and is a second slanted sidewall, the portion of the bottom surface is directly connected to the first slanted sidewall and the second slanted sidewall, and the portion of the bottom surface, the first slanted sidewall, and the second slanted sidewall together form a sawtooth surface.

9. The semiconductor device structure as claimed in claim 8 , wherein a first minimum width of the second opening is greater than a second minimum width of the first opening.

10. The semiconductor device structure as claimed in claim 8 , wherein the capacitor has a recess in the first opening and the second opening.

11. The semiconductor device structure as claimed in claim 10 , further comprising:
a conductive layer filled in the recess and electrically connected to the capacitor.

12. The semiconductor device structure as claimed in claim 11 , wherein a first top surface of the conductive layer is aligned with a second top surface of the capacitor.

13. A semiconductor device structure, comprising:
a substrate;
a conductive structure in or over the substrate;
a first dielectric layer over the substrate, wherein the first dielectric layer has a first opening exposing the conductive structure;
a second dielectric layer over the first dielectric layer, wherein the second dielectric layer has a second opening connected to the first opening and exposing the conductive structure, the second dielectric layer has a bottom surface, a portion of the bottom surface is located directly above the first opening, and the first dielectric layer and the second dielectric layer are made of a same material;
a capacitor covering a first inner wall of the first opening, a second inner wall of the second opening, a bottom surface of the second dielectric layer, and a top surface of the conductive structure, wherein the capacitor is electrically connected to the conductive structure, the capacitor has a recess in the first opening and the second opening, the first inner wall of the first opening starts at a top of the first dielectric layer, ends at a bottom of the first dielectric layer, and is a first slanted sidewall, the second inner wall of the second opening starts at a top of the second dielectric layer, ends at a bottom of the second dielectric layer, and is a second slanted sidewall, the portion of the bottom surface is directly connected to the first slanted sidewall and the second slanted sidewall, and the portion of the bottom surface, the first slanted sidewall, and the second slanted sidewall together form a sawtooth surface; and
an insulating layer filled in the recess.

14. The semiconductor device structure as claimed in claim 13 , wherein a first top surface of the insulating layer is aligned with a second top surface of the capacitor.

15. The semiconductor device structure as claimed in claim 13 , wherein a first top surface of the insulating layer, a second top surface of the capacitor, and a third top surface of the second dielectric layer are aligned with each other.

16. The semiconductor device structure as claimed in claim 13 , wherein the capacitor is in direct contact with the conductive structure and the insulating layer.

17. The semiconductor device structure as claimed in claim 13 , wherein the insulating layer cove

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Tai-Shin
• Chang Che-Cheng

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title