Graphics processor register renaming mechanism

Patent metadata

Field	Value
Publication number	US-10565670-B2
Application number	US-201615281276-A
Country	US
Kind code	B2
Filing date	Sep 30, 2016
Priority date	Sep 30, 2016
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a plurality of execution units to process graphics context data and a register file having a plurality of registers to store the graphics context data; and register renaming logic to facilitate dynamic renaming of the plurality of registers by logically partitioning the plurality of registers in the register file into a set of fixed registers and a set of shared registers.

First claim

What is claimed is:

1. An apparatus comprising:
a graphics processor including:
a plurality of execution units to process graphics context data;
a register file having a plurality of registers to store the graphics context data; and
register renaming logic to facilitate dynamic renaming of the plurality of registers by logically partitioning the plurality of registers in the register file into a set of fixed registers and a set of shared registers, wherein a size of the set of shared registers is adjustable and larger than the set of fixed registers, wherein renaming includes dynamically renaming a variable assigned to a shared register to a unified physical register file that is shared by hardware contexts associated with an execution unit, wherein the variable is assigned during kernel execution.

2. The apparatus of claim 1 , wherein the graphics processor further comprises:
a renaming table to store the renaming of each register within the set of shared registers to a shared physical register, wherein the set of shared registers contains greater than 64 registers; and
decoding logic to perform register renaming of operands from the set of fixed registers and operands from the set of shared registers during execution of the context via the renaming table.

3. The apparatus of claim 2 , wherein the register renaming comprises:
determining whether a register identification (ID) of an operand of the context is less than a starting range of the set of shared registers; and
accessing the set of fixed registers to perform an operation on the operand upon determining that the operand is less than the starting range of the set of shared registers.

4. The apparatus of claim 3 , wherein the register renaming further comprises:
determining whether the operand is a source operand upon determining that the operand is greater than the starting range of the set of shared registers;
accessing the renaming table to find a physical register corresponding to the register ID upon determining that the operand is a source operand; and
fetching the operand from the set of shared registers.

5. The apparatus of claim 4 , wherein the register renaming further comprises:
determining whether a new shared register can be acquired upon determining that the operand is not a source operand; and
storing a mapping of the shared register to a physical register ID in the renaming table upon determining that the new shared register can be acquired.

6. The apparatus of claim 5 , wherein the register renaming further comprises stalling the context upon determining that the new shared register is not acquired.

7. The apparatus of claim 1 , wherein renaming includes assigning first variables having long live ranges to the set of fixed registers, and assigning second variables having short live ranges to the set of shared registers.

8. The apparatus of claim 7 , wherein the register renaming logic facilitates the generation of spill code upon a determination that register assignments exceed the plurality of registers on the register file.

9. The apparatus of claim 1 , wherein the register renaming logic provides instructions as to when a register in the set of shared registers is to be released, wherein a location of a local variable is marked to be released after a final last use before a new full definition, wherein a location of a global variable is marked to be released at an immediate post-dominator in a control flow graph for basic blocks that include last uses of a previous definition.

10. A graphics processor comprising:
a plurality of execution units to process graphics context data;
a register file having a plurality of registers to store the graphics context data;
decoding logic to perform register renaming of operands from a set of fixed registers and
operands from a set of shared registers during execution of a context, wherein a size of the set of shared registers is adjustable and larger than the set of fixed registers; and
a renaming table to store the renaming of each register within the set of shared registers to a shared physical register, wherein renaming includes dynamically renaming a variable assigned to a shared register to a unified physical register file that is shared by hardware contexts associated with an execution unit, wherein the variable is assigned during kernel execution.

11. The graphics processor of claim 10 , wherein the register renaming comprises:
determining whether a register identification (ID) of an operand of the context is less than a starting range of the set of shared registers; and
accessing the set of fixed registers to perform an operation on the operand upon determining that the operand is less than the starting range of the set of shared registers.

12. The graphics processor of claim 11 , wherein the register renaming further comprises:
determining whether the operand is a source operand upon determining that the operand is greater than the starting range of the set of shared registers;
accessing the renaming table to find a physical register corresponding to the register ID upon determining that the operand is a source operand; and
fetching the operand from the set of shared registers.

13. The graphics processor of claim 12 , wherein the register renaming further comprises:
determining whether a new shared register can be acquired upon determining that the operand is not a source operand; and
storing a mapping of the shared register to a physical register ID in the renaming table upon determining that the new shared register can be acquired.

14. The graphics processor of claim 13 , wherein the register renaming further comprises stalling the context upon determining that the new shared register is not acquired.

15. The graphics processor of claim 10 , wherein the register renaming logic is further to facilitate dynamic renaming of the plurality of registers by logically partitioning the plurality of registers in the register file into a set of fixed registers and a set of shared registers, wherein the set of shared registers contains more than 64 registers.

16. A method comprising:
receiving graphics context operands at a graphics processor;
decoding the operands; and
performing register renaming of the operands from a set of fixed registers and operands from a set of shared registers during execution of the graphics contexts, wherein a size of the set of shared registers is adjustable and larger than the set of fixed registers, wherein renaming includes dynamically renaming a variable assigned to a shared register to a unified physical register file that is shared by hardware contexts associated with an execution unit, wherein the variable is assigned during kernel execution.

17. The method of claim 16 , wherein the register renaming comprises: determining whether a register identification (ID) of an operand of the context is less than a starting range of the set of shared registers; and
accessing the set of fixed registers to perform an operation on the operand upon determining that the operand is less than the starting range of the set of shared registers.

18. The method of claim 17 , wherein the register renaming further comprises:
determining whether the operand is a source operand upon determining that the operand is greater than the starting range of the set of shared registers, wherein the set of shared registers contains more than 64 registers;
accessing the renaming table to find a physical register corresponding to the register ID upon determining that the operand is a source operand; and
f

Assignees

• Intel Corp

Inventors

• Chen Kaiyu
• Lueh Guei-Yuan
• Maiyuran Subramaniam

Classifications

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30178

  of compressed or encrypted instructions · CPC title

• G06F9/384

  Register renaming · CPC title

• G06T1/60

  Memory management · CPC title

• G06F9/30149

  of variable length instructions · CPC title