Communication between dataflow processing units and memories

Patent metadata

Field	Value
Publication number	US-10564929-B2
Application number	US-201715665631-A
Country	US
Kind code	B2
Filing date	Aug 1, 2017
Priority date	Sep 1, 2016
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

A combination of memory units and dataflow processing units is disclosed for computation. A first memory unit is interposed between a first dataflow processing unit and a second dataflow processing unit. Operations for a dataflow graph are allocated across the first dataflow processing unit and the second dataflow processing unit. The first memory unit passes data between the first dataflow processing unit and the second dataflow processing unit to execute the dataflow graph. The first memory unit is a high bandwidth, shared memory device including a hybrid memory cube. The first dataflow processing unit and second dataflow processing unit include a plurality of circular buffers containing instructions for controlling data transfer between the first dataflow processing unit and second dataflow processing unit. Additional dataflow processing units and additional memory units are included for additional functionality and efficiency.

First claim

What is claimed is:

1. An apparatus for computation comprising:
a first dataflow processing unit;
a second dataflow processing unit;
a first plurality of circular buffers, wherein the first plurality of circular buffers is included in the first dataflow processing unit and contains instructions for controlling data transfer between the first dataflow processing unit and the second dataflow processing unit; and
a first memory unit interposed between the first dataflow processing unit and the second dataflow processing unit wherein operations for a dataflow graph are allocated across the first dataflow processing unit and the second dataflow processing unit and wherein the first memory unit passes data between the first dataflow processing unit and the second dataflow processing unit to execute the dataflow graph.

2. The apparatus of claim 1 wherein the first memory unit comprises a shared memory device.

3. The apparatus of claim 1 wherein the first memory unit comprises a hybrid memory cube.

4. The apparatus of claim 1 wherein the second dataflow processing unit comprises a second plurality of circular buffers containing instructions for controlling data transfer between the first dataflow processing unit and the second dataflow processing unit using the first memory unit.

5. The apparatus of claim 1 wherein the first dataflow processing unit is coupled to the first memory unit via a first link.

6. The apparatus of claim 5 wherein the first link accesses a plurality of FIFOs within the first memory unit.

7. The apparatus of claim 6 wherein the plurality of FIFOs is configured using DRAM memory.

8. The apparatus of claim 7 wherein the plurality of FIFOs each have an address pointer to sequence through a FIFO from the plurality of FIFOs.

9. The apparatus of claim 6 wherein the plurality of FIFOs is statically defined.

10. The apparatus of claim 9 wherein definition for the plurality of FIFOs is accomplished at compile time based on the dataflow graph.

11. The apparatus of claim 5 wherein the first dataflow processing unit uses a write port within the first link to send data to the first memory unit.

12. The apparatus of claim 1 wherein the second dataflow processing unit is coupled to the first memory unit via a second link.

13. The apparatus of claim 12 wherein the second dataflow processing unit uses a read port within the second link to receive data from the first memory unit.

14. The apparatus of claim 12 wherein the second link accesses a plurality of FIFOs within the first memory unit.

15. The apparatus of claim 1 further comprising a third dataflow processing unit coupled to the first memory unit wherein the third dataflow processing unit accesses the first memory unit through a third link.

16. The apparatus of claim 15 further comprising a fourth dataflow processing unit coupled to the first memory unit wherein the fourth dataflow processing unit accesses the first memory unit through a fourth link.

17. The apparatus of claim 1 further comprising a second memory unit interposed between the first dataflow processing unit and the second dataflow processing unit.

18. The apparatus of claim 17 further comprising a third memory unit interposed between the first dataflow processing unit and the second dataflow processing unit.

19. The apparatus of claim 18 further comprising a fourth memory unit interposed between the first dataflow processing unit and the second dataflow processing unit.

20. The apparatus of claim 19 further comprising a third dataflow processing unit and a fourth dataflow processing unit.

21. The apparatus of claim 20 wherein each of the first memory unit, the second memory unit, the third memory unit, and the fourth memory unit access each of the first dataflow processing unit, the second dataflow processing unit, the third dataflow processing unit, and the fourth dataflow processing unit on different links.

22. The apparatus of claim 1 wherein the first dataflow processing unit, the second dataflow processing unit, and the first memory unit comprise a deep learning machine.

23. A processor-implemented method for computation comprising:
obtaining data from a first dataflow processing unit, wherein the first dataflow processing unit includes a plurality of circular buffers containing instructions to control dataflow;
sending the data from the first dataflow processing unit through a first memory unit interposed between the first dataflow processing unit and a second dataflow processing unit wherein operations for a dataflow graph are allocated across the first dataflow processing unit and the second dataflow processing unit and wherein the first memory unit passes data between the first dataflow processing unit and the second dataflow processing unit to execute the dataflow graph; and
receiving the data into the second dataflow processing unit.

Assignees

• Wave Computing Inc

Inventors

• Nicol Christopher John
• Meyer Derek William

Classifications

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F15/82

  data or demand driven · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F13/1663

  Access to shared memory · CPC title

• G06N20/00 Primary

  Machine learning · CPC title