Semiconductor memory device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10559570-B2
Application number	US-201815889161-A
Country	US
Kind code	B2
Filing date	Feb 5, 2018
Priority date	Jan 18, 2018
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, and isolation structures. The bit line structures, the storage node contacts, and the isolation structures are disposed on the semiconductor substrate. Each bit line structure is elongated in a first direction, and the bit line structures are repeatedly disposed in a second direction. Each storage node contact and each isolation structure are disposed between two of the bit line structures adjacent to each other in the second direction. Each storage node contact is disposed between two of the isolation structures disposed adjacent to each other in the first direction. Each isolation structure includes at least one first portion elongated in the first direction and partially disposed between one of the bit line structures and one of the storage node contacts adjacent to the isolation structure in the second direction.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a semiconductor substrate;
bit line structures disposed on the semiconductor substrate, wherein each of the bit line structures is elongated in a first direction, and the bit line structures are repeatedly disposed in a second direction, wherein the second direction is substantially orthogonal to the first direction;
storage node contacts disposed on the semiconductor substrate, wherein each of the storage node contacts is disposed between two of the bit line structures disposed adjacent to each other in the second direction;
isolation structures disposed on the semiconductor substrate, wherein each of the isolation structures is disposed between two of the bit line structures disposed adjacent to each other in the second direction, each of the storage node contacts is disposed between two of the isolation structures disposed adjacent to each other in the first direction, and each of the isolation structures comprises two first portions and a second portion disposed between the two first portions in the second direction, wherein each of the first portions is elongated in the first direction and partially disposed between one of the bit line structures disposed adjacent to the isolation structure and one of the storage node contacts disposed adjacent to the isolation structure in the second direction, wherein each of the first portions is disposed between the second portion and one of the bit line structures disposed adjacent to the isolation structure in the second direction; and
a plurality of word line structures having extending direction thereof in the second direction.

2. The semiconductor memory device according to claim 1 , wherein a length of each of the first portions in the first direction is longer than a length of the second portion in the first direction.

3. The semiconductor memory device according to claim 1 , wherein a part of one of the storage node contacts is disposed between the first portions of only one of the isolation structures disposed adjacent to the storage node contact.

4. The semiconductor memory device according to claim 1 , wherein each of the storage node contacts comprises:
a main portion; and
two protruding portions disposed at two opposite sides of the main portion in the second direction, wherein each of the protruding portions extends towards one of the bit line structures disposed adjacent to the storage node contact, and is substantially a square structure, and the main portion has a rectangular structure with chamfered corners, under a top view diagram, respectively.

5. The semiconductor memory device according to claim 4 , wherein each of the protruding portions of each of the storage node contacts is partially disposed between the first portions of two of the isolation structures disposed adjacent to the storage node contact in the first direction, wherein the two protruding portions of a plurality of storage node contacts are arranged along the second direction.

6. The semiconductor memory device according to claim 1 , further comprising a liner surrounding each of the storage node contacts, wherein the liner is partly disposed between each of the storage node contacts and one of the bit line structures disposed adjacent to the storage node contact in the second direction and partly disposed between each of the storage node contacts and one of the isolation structures disposed adjacent to the storage node contact in the first direction.

7. The semiconductor memory device according to claim 6 , wherein the liner disposed between each of the storage node contacts and one of the bit line structures disposed adjacent to the storage node contact in the second direction is disposed between the first portions of two of the isolation structures disposed adjacent to the storage node contact in the first direction.

8. The semiconductor memory device according to claim 1 , wherein each of the isolation structures comprises an I-shaped structure having a shape resemble the letter I in a top view diagram of the semiconductor memory device.

9. The semiconductor memory device according to claim 1 , wherein the first portion of the isolation structure has curved corner surfaces at the ends thereof toward the storage node contacts, and also having a straight flat surface toward the bit line structure, under a plan view diagram.

10. The semiconductor memory device according to claim 4 , wherein the plurality of storage node contacts are arranged in a head-to-tail configuration, with the substantially square structures of the two protruding portions being the head and tail, respectively.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Nagai Yukihiro

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H01L21/31111

  Electricity · mapped topic