Methods of fabricating semiconductor devices

Patent metadata

Field	Value
Publication number	US-9607994-B2
Application number	US-201514755690-A
Country	US
Kind code	B2
Filing date	Jun 30, 2015
Priority date	Oct 18, 2012
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide. A storage node contact plug hole can be formed so that the etch stop pattern and the separate spacer form a portion of a sidewall of the storage node contact plug hole spaced apart from the bit line contact. The storage node contact plug hole can be cleaned to remove a natural oxide formed in the storage node contact plug hole. Related devices are also disclosed.

First claim

What is claimed:

1. A method of forming a semiconductor device comprising:
removing a portion of a substrate to form a bitline node contact hole;
forming a bitline contact in the bitline node contact hole;
forming an etch stop pattern and a separate spacer on a sidewall of the bitline contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide;
forming a storage node contact plug hole so that the etch stop pattern and the separate spacer form a portion of a sidewall of the storage node contact plug hole spaced apart from the bitline contact; and
cleaning the storage node contact plug hole to remove a natural oxide formed in the storage node contact plug hole.

2. The method of claim 1 wherein the etch stop pattern includes an uppermost a curved surface in contact with a lowest most portion of the separate spacer.

3. The method of claim 1 wherein the spacer further comprises a gap region.

4. The method of claim 3 wherein the gap region comprises an air-gap region between a sidewall thereof and the bitline above the etch stop pattern.

5. The method of claim 3 wherein the air-gap region exposes a sidewall of the bitline.

6. The method of claim 5 wherein a total width of the spacer is substantially equal to a maximum width of the etch stop pattern.

7. The method of claim 1 wherein the etch stop pattern and the separate spacer comprise identical materials.

8. The method of claim 1 wherein forming an etch stop pattern is preceded by:
forming spaced-apart first and second doped regions in the substrate;
forming an insulating layer on the substrate to define an opening exposing the second doped region; and
removing the portion of the substrate exposed by the opening to form the bitline node contact hole.

9. The method of claim 1 wherein forming an etch stop pattern and a separate spacer on a sidewall of a bitline contact further comprises:
forming a second spacer between the separate spacer and the sidewall of the bitline contact, in contact with the bitline node contact plug and the etch stop pattern.

10. The method of claim 9 further comprising:
forming a storage node contact plug in the storage node contact plug hole.

11. A method of fabricating a semiconductor device, comprising:
forming spaced-apart first and second doped regions in a substrate;
forming an insulating layer on the substrate to define an opening exposing the second doped region;
removing a portion of the substrate exposed by the opening to form a bitline node contact hole, the bitline node contact hole formed to have a bottom surface lower than a top surface of the substrate;
forming a bit line and a bitline node contact plug that are provided on the insulating layer and in the bitline node contact hole, respectively;
forming a spacer in the bitline node contact hole; and
forming a storage node contact plug electronically connected to the first doped region,
wherein the bit line and the bitline node contact plug are spaced apart from the storage node contact plug with the spacer interposed therebetween, and
wherein at least a portion of the spacer is formed of a material having an etch selectivity with respect to a natural oxide layer.

12. The method of claim 11 , wherein forming the spacer comprises:
forming a etch stop pattern to fill at least a portion of the bitline node contact hole;
forming a first sub-spacer to cover a sidewall of the bit line; and
forming a second sub-spacer to cover a sidewall of the first sub-spacer and in contact with a top surface of the etch stop pattern.

13. The method of claim 11 , wherein forming the storage node contact plug comprises:
removing at least a portion of the insulating layer adjacent to the spacer to form a storage node contact hole exposing the first doped region;
removing a natural oxide layer from the storage node contact hole; and
forming a storage node contact plug to fill the storage node contact hole.

14. The method of claim 11 , further comprising:
forming, a device isolation layer in the substrate to define an active region that includes the first and second doped regions,
wherein the bitline node contact hole extends to a portion of the device isolation layer adjacent to the second doped region.

15. A method of fabricating a semiconductor device, comprising:
forming a first doped region and a second doped region in a substrate, the first and second doped regions being spaced apart from each other;
forming an insulating layer on the substrate to define an opening exposing the second doped region;
removing a portion of the substrate exposed by the opening to form a bitline node contact hole;
forming a bit line and a bitline node contact plug that are provided on the insulating layer and in the bitline node contact hole, respectively;
forming a spacer to cover sidewalls of the bit line and the bitline node contact plug; and
forming a storage node contact plug to be in contact with the spacer and the first doped region,
wherein forming spacer comprises:
forming a first sub-spacer to cover the sidewall of the bit line;
forming the etch stop pattern to fill the bitline node contact hole.

16. The method of claim 15 , wherein the forming of the spacer further comprises:
forming a second sub-spacer to cover a sidewall of the first sub-spacer and be in contact with a top surface of the etch stop pattern.

17. The method of claim 15 , further comprising selectively removing the first sub-spacer to form an air-gap region.

18. The method of claim 16 , wherein the forming of the storage node contact plug comprises:
removing at least a portion of the insulating layer adjacent to the spacer to form a storage node contact hole exposing the first doped region; and
forming a storage node contact plug to fill the storage node contact hole,
wherein the storage node contact hole is formed to expose side surfaces of the etch stop pattern and the second sub-spacer but not to expose the first sub-spacer.

19. The method of claim 18 , further comprising removing a natural oxide layer from the storage node contact hole,
wherein each of the second sub-spacer and the etch stop pattern is formed of a material having an etch selectivity with respect to the natural oxide layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Keunnam
• Park Sunyoung
• Yeom Kyehee
• Jang Hyeon-Woo
• Jeong Jin-Won
• Cho Changhyun
• Hong Hyeongsun

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/46

  comprising air gaps · CPC title