Power consumption management for communication bus

Patent metadata

Field	Value
Publication number	US-10558254-B2
Application number	US-201715477042-A
Country	US
Kind code	B2
Filing date	Apr 1, 2017
Priority date	Apr 1, 2017
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.

First claim

The invention claimed is:

1. A graphics multiprocessor, comprising:
an instruction cache to receive a stream of instructions;
an instruction unit to execute the stream of instructions;
a general-purpose graphics processing compute block comprising a plurality of graphics processing cores;
a shared memory communicatively coupled to the plurality of graphics processing cores; and
a processor to, for each graphics processing core in a subset of graphics processing cores in the plurality of graphics processing cores:
receive data for a current write operation to the shared memory communicatively coupled at least one of the plurality of graphics processing cores;
determine a number of bits in the received data for the current write operation to the shared memory which have changed from a previous write operation to the memory; and
in response to a determination that the number of bits in the received data for the current write operation to the shared memory which have changed from a previous write operation to the memory exceeds a threshold, to:
toggle a plurality of bits in the data for the current write operation to create an encoded data set;
set an indicator bit to a value which indicates that the plurality of bits have been toggled; and
transmit the encoded data set and the indicator bit on a communication bus between the at least one of the plurality of graphics processing cores and the shared memory,

wherein the threshold is an adaptive threshold which is set based at least in part on one or more characteristics of the data being transmitted on the communication bus.

2. The graphics multiprocessor of claim 1 , further comprising:
a memory interface communicatively coupled to at least one of the plurality of graphics processor cores, the memory interface comprising a plurality of partition units.

3. The graphics multiprocessor of claim 2 , wherein the processing circuitry comprises:
a bitwise inverter to invert the input from the data for the current write operation to generate an inverted data set;
an array of flip flops which holds the data for the previous write operation; and
a compare logic to generate a control signal when the number of bits in the received data for the current write operation to the shared memory which have changed from a previous write operation to the memory exceeds a threshold.

4. The graphics multiprocessor of claim 3 , wherein the processing circuitry further comprises:
a multiplexer to output one of the inverted data set or the data for the current write operation based on the control signal from the compare logic.

5. The graphics multiprocessor of claim 4 , further comprising processing circuitry to:
forward the control signal on the communication bus as the indicator bit.

6. The graphics multiprocessor of claim 5 , further comprising processing circuitry to:
receive the one of the inverted data set or the data for the current write operation and the indicator bit from the communication bus; and
in response to a determination that the indictor bit is set to indicate that the inverted data set has been received, to:
toggle a plurality of bits in the inverted data set to generate a write data set; and
write the write data set to the shared memory.

7. The graphics multiprocessor of claim 5 , further comprising processing circuitry to:
receive the one of the inverted data set or the data for the current write operation and the indicator bit from the communication bus; and
in response to a determination that the indictor bit is not set to indicate that the inverted data set has been received, to:
write the data for the current write operation to the shared memory.

8. An electronic device, comprising:
an instruction cache to receive a stream of instructions;
an instruction unit to execute the stream of instructions;
a general-purpose graphics processing compute block comprising a plurality of graphics processing cores;
a shared memory communicatively coupled to the plurality of graphics processing cores; and
a processor to, for each graphics processing core in a subset of graphics processing cores in the plurality of graphics processing cores:
receive data for a current write operation to the shared memory communicatively coupled at least one of the plurality of graphics processing cores;
determine a number of bits in the received data for the current write operation to the shared memory which have changed from a previous write operation to the shared memory; and
in response to a determination that the number of bits in the received data for the current write operation to the shared memory which have changed from a previous write operation to the memory exceeds a threshold, to:
toggle a plurality of bits in the data for the current write operation to create an encoded data set;
set an indicator bit to a value which indicates that the plurality of bits have been toggled; and
transmit the encoded data set and the indicator bit on a communication bus between the at least one of the plurality of graphics processing cores and the shared memory,

wherein the threshold is an adaptive threshold which is set based at least in part on one or more characteristics of the data being transmitted on the communication bus; and
a computer readable memory communicatively coupled to the plurality of graphics processing cores.

9. The electronic device of claim 8 , further comprising:
a memory interface communicatively coupled to at least one of the plurality of graphics processing cores, the memory interface comprising a plurality of partition units.

10. The electronic device of claim 9 , wherein the processing circuitry comprises:
a bitwise inverter to invert the input from the data for the current write operation to generate an inverted data set;
an array of flip flops which holds the data for the previous write operation; and
a compare logic to generate an control signal when the number of bits in the received data for the current write operation to the shared memory which have changed from a previous write operation to the shared memory exceeds a threshold.

11. The electronic device of claim 10 , wherein the processing circuitry further comprises:
a multiplexer to output one of the inverted data set or the data for the current write operation based on the control signal from the compare logic.

12. The electronic device of claim 11 , further comprising processing circuitry to:
forward the control signal on the communication bus as the indicator bit.

13. The electronic device of claim 12 , further comprising processing circuitry to:
receive the one of the inverted data set or the data for the current write operation and the indicator bit from the communication bus; and
in response to a determination that the indictor bit is set to indicate that the inverted data set has been received, to:
toggle a plurality of bits in the inverted data set to generate a write data set; and
write the write data set to the shared memory.

14. The electronic device of claim 12 , further comprising processing circuitry to:
receive the one of the inverted data set or the data for the current write operation and the indicator bit from the communication bus; and
in response to a determination that the indictor bit is not set to indicate that the inverted data set has been received, to:
write the data for the current write operation to the shared memory.

15. A graphics multiprocessor, comprising:
an instruction cache to receive a stream of instructions;
an instruction unit to execute the stream of instructions;
a general-purpose graphics pr

Assignees

• Intel Corp

Inventors

• Appu Abhishek R
• Koker Altug
• Hoekstra Eric J
• Veernapu Kiran C
• Surti Prasoonkumar
• Ranganathan Vasanth
• Sinha Kamal
• Vembu Balaji
• Asperheim Eric J
• Jahagirdar Sanjeev S
• Ray Joydeep

Classifications

• G06F1/3225 Primary

  of memory devices · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F1/3253

  Power saving in bus · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title