Amplifier circuit having controllable output stage

Patent metadata

Field	Value
Publication number	US-10555269-B2
Application number	US-201816121644-A
Country	US
Kind code	B2
Filing date	Sep 5, 2018
Priority date	Nov 24, 2017
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

The present invention provides an amplifier circuit, wherein the amplifier circuit includes a DAC, an output stage and a detector. In the operations of the amplifier circuit, the DAC is arranged for performing a digital-to-analog converting operation upon a digital input signal to generate an analog signal, the output stage is arranged for receiving the analog signal to generate an output signal, and the detector is arranged for detecting a characteristic of the input signal, and referring to the characteristic of the input signal to generate at least one control signal to adjust the output stage at a zero-crossing point of the output signal.

First claim

What is claimed is:

1. An amplifier circuit, comprising:
a digital-to-analog converter (DAC), for performing a digital-to-analog converting operation upon a digital input signal to generate an analog signal;
an output stage, coupled to the DAC, for receiving the analog signal to generate an output signal; and
a detector, coupled to the output stage, for detecting a characteristic of the input signal, and referring to the characteristic of the input signal to generate at least one control signal to adjust a quiescent current of the output stage at a zero-crossing point of the output signal.

2. The amplifier circuit of claim 1 , further comprising:
a delay circuit, for delaying the digital input signal to generate a delayed digital input signal;
wherein the DAC performs the digital-to-analog converting operation upon the delayed digital input signal to generate the analog signal.

3. The amplifier circuit of claim 1 , wherein the detector refers to the strength of the input signal to generate the at least one control signal to adjust a size of the output stage at the zero-crossing point of the output signal.

4. The amplifier circuit of claim 3 , wherein the output stage comprises:
a plurality of segments, wherein each of the segments selectively receives the analog signal via at least one switch;
wherein the detector generates a plurality of control signals to control the switches of the segments, respectively.

5. The amplifier circuit of claim 4 , wherein the analog signal comprises a first signal and a second signal, and each of the segments comprises:
a P-type transistor, for selectively receives the first signal via a first switch; and
an N-type transistor, coupled to the P-type transistor via a node, for selectively receives the second signal via a second switch;
wherein the nodes of the segments are connected together and generate the output signal.

6. The amplifier circuit of claim 3 , wherein a bias current of the output stage is fixed.

7. The amplifier circuit of claim 1 , wherein the detector refers to the characteristic of the input signal to generate the at least one control signal to adjust a bias current of the output stage at the zero-crossing point of the output signal.

8. The amplifier circuit of claim 7 , wherein the analog signal comprises a first signal and a second signal, and the output stage comprises:
a P-type transistor, for receiving the first signal; and
an N-type transistor, coupled to the P-type transistor, for receiving the second signal;
wherein the detector generates the at least one control signal to adjust bias voltages of the P-type transistor and the N-type transistor.

9. The amplifier circuit of claim 7 , wherein the analog signal comprises a first signal and a second signal, and the output stage comprises:
a plurality of segments, wherein each of the segments comprises:
a P-type transistor, for receiving the first signal; and
an N-type transistor, coupled to the P-type transistor via a node, for receiving the second signal, wherein the nodes of the segments are connected together and generate the output signal;
wherein the detector generates a plurality of control signals to adjust bias voltages of the P-type transistor and the N-type transistor of the segments, respectively.

10. The amplifier circuit of claim 7 , wherein a size of the output stage is fixed.

11. The amplifier circuit of claim 1 , wherein the input signal is an audio signal, and the characteristic of the input signal is a strength of the input signal or a volume of the input signal.

12. The amplifier circuit of claim 1 , wherein the output stage is a Class-AB output stage.

13. The amplifier circuit of claim 1 , wherein the output stage is a Class-D output stage.

14. An amplifier circuit, comprising:
a delay circuit, for delaying an input signal to generate a delayed input signal;
an output stage, coupled to the delay circuit, for receiving the delayed input signal to generate an output signal; and
a detector, coupled to the output stage, for detecting a characteristic of the input signal, and referring to the characteristic of the input signal to generate at least one control signal to adjust a quiescent current of the output stage at a zero-crossing point of the output signal.

15. The amplifier circuit of claim 14 , wherein the detector refers to the characteristic of the input signal to generate the at least one control signal to adjust a size of the output stage at the zero-crossing point of the output signal.

16. The amplifier circuit of claim 15 , wherein a bias current of the output stage is fixed.

17. The amplifier circuit of claim 14 , wherein the detector refers to the characteristic of the input signal to generate the at least one control signal to adjust a bias current of the output stage at the zero-crossing point of the output signal.

18. The amplifier circuit of claim 17 , wherein a size of the output stage is fixed.

19. The amplifier circuit of claim 14 , wherein the input signal is an audio signal, and the characteristic of the input signal is a strength of the input signal or a volume of the input signal.

20. The amplifier circuit of claim 14 , wherein the output stage is a Class-AB output stage or a Class-D output stage.

Assignees

• Mediatek Inc

Inventors

• Wen Sung-Han
• Chen Ya-Chi

Classifications

• H03F2203/30132

  the push transistor being gated by a switching element · CPC title

• H04W52/52 Primary

  using AGC [Automatic Gain Control] circuits or amplifiers · CPC title

• H03F3/217

  Class D power amplifiers; Switching amplifiers · CPC title

• H03F1/3217

  in single ended push-pull amplifiers · CPC title

• H03F1/025

  by using a signal derived from the input signal · CPC title