Circuits and methods for bi-directional data communication over isolation channels

Patent metadata

Field	Value
Publication number	US-10554456-B2
Application number	US-201816102910-A
Country	US
Kind code	B2
Filing date	Aug 14, 2018
Priority date	Aug 23, 2017
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

In a general aspect, a data communication circuit can include a transmitter configured to transmit a first digital bit stream via a first unidirectional isolation channel. The data communication circuit can further include a receiver configured to receive a second digital bit stream via a second unidirectional isolation channel. The first unidirectional isolation channel and the second unidirectional isolation channel can be defined on a common dielectric substrate. The data communication circuit can further include a crosstalk suppression circuit configured to provide at least one negative feedback signal to suppress crosstalk between the transmitter and the receiver due to parasitic capacitive coupling between the first unidirectional isolation channel and the second unidirectional isolation channel in the common dielectric substrate.

First claim

What is claimed is:

1. A data communication circuit comprising:
a differential transmitter configured to transmit a first digital bit stream via a first differential unidirectional isolation channel;
a differential receiver configured to receive a second digital bit stream via a second differential unidirectional isolation channel, the first differential unidirectional isolation channel and the second differential unidirectional isolation channel being defined on a common dielectric substrate; and
a crosstalk suppression circuit being configured to provide:
via a first adjustable capacitance circuit, a first negative feedback signal applied between a positive output terminal of the differential transmitter and a negative input terminal of the differential receiver; and
via a second adjustable capacitance circuit, a second negative feedback signal applied between a negative output terminal of the differential transmitter and a positive input terminal of the differential receiver,
the first negative feedback signal and the second negative feedback signal being configured to suppress crosstalk between the differential transmitter and the differential receiver due to parasitic capacitive coupling between the first differential unidirectional isolation channel and the second differential unidirectional isolation channel in the common dielectric substrate,

the data communication circuit being configured to adjust respective capacitances of the first adjustable capacitance circuit and the second adjustable capacitance circuit based on a calibration signal, the calibration signal providing an indication of the parasitic capacitive coupling between the first differential unidirectional isolation channel and the second differential unidirectional isolation channel.

2. The data communication circuit of claim 1 , wherein the differential receiver includes an LC resonant circuit having a corner frequency, the LC resonant circuit being configured to attenuate signals with frequencies below the corner frequency.

3. The data communication circuit of claim 1 , wherein the differential transmitter is configured to transmit the first digital bit stream using an On/Off keyed radio-frequency carrier signal.

4. The data communication circuit of claim 1 , wherein the second digital bit stream is an On/Off keyed radio-frequency signal, the differential receiver including:
a full-wave rectifier configured to detect an envelope of the On/Off keyed radio-frequency signal; and
a comparator configured to convert the detected envelope to a baseband digital bit stream.

5. The data communication circuit of claim 1 , further comprising an encoder coupled with the differential transmitter, the encoder being configured to provide a Manchester-encoded baseband digital bit stream to the differential transmitter for transmission as the first digital bit stream.

6. The data communication circuit of claim 1 , wherein the differential receiver includes a comparator,
a threshold of the comparator being adjustable based on a clock signal received via the second differential unidirectional isolation channel.

7. The data communication circuit of claim 4 , wherein:
the comparator includes a Schmitt trigger; and
the data communication circuit is configured to calibrate a threshold of the Schmitt trigger to an average amplitude of a 50 percent duty cycle square wave envelope detection signal produced by the full-wave rectifier.

8. The data communication circuit of claim 4 , wherein the baseband digital bit stream is an encoded digital bit stream, the data communication circuit further comprising:
a decoder configured to:
recover a clock signal from the encoded digital bit stream, the clock signal being recovered using a delay that is proportional to a period of the clock signal; and
decode the encoded digital bit stream using the recovered clock signal to produce a decoded digital bit stream.

9. The data communication circuit of claim 5 , further comprising a serial programmable interface (SPI) coupled with the encoder, the Manchester-encoded baseband digital bit stream including one of:
data bits provided by the SPI sequentially interleaved with gate driver control bits;
data bits provided by the SPI sequentially interleaved with gate driver status bits.

10. The data communication circuit of claim 6 , wherein the differential receiver includes:
a full-wave rectifier configured to detect an envelope of a differential On/Off keyed radio-frequency signal received via the second differential unidirectional isolation channel, the full-wave rectifier and the comparator of the differential receiver being configured to convert the differential On/Off keyed radio-frequency signal to a baseband digital bit stream.

11. The data communication circuit of claim 8 , wherein the decoded digital bit stream is a serialized digital bit stream, the data communication circuit further comprising:
a deserializer configured to, using the recovered clock signal, deserialize the serialized digital bit stream to a plurality of output bits.

12. The data communication circuit of claim 8 , wherein the delay is determined from a 50 percent duty cycle square wave envelope detection signal produced by the full-wave rectifier.

13. The data communication circuit of claim 10 , wherein the baseband digital bit stream is an encoded digital bit stream, the data communication circuit further comprising:
a decoder coupled with the differential receiver, the decoder being configured to:
recover a clock signal from the encoded digital bit stream, the recovered clock signal being recovered using a delay that is proportional to a period of the clock signal; and
decode the encoded digital bit stream using the recovered clock signal to produce a decoded digital bit stream.

14. A method comprising:
adjusting, by a first data communication circuit, a capacitance of a first crosstalk suppression circuit included in the first data communication circuit, the first crosstalk suppression circuit being configured to suppress crosstalk between a transmitter and a receiver of the first data communication circuit;
in response to determining that adjustment of the capacitance of the first crosstalk suppression circuit has been completed, adjusting, by a second data communication circuit, a capacitance of a second crosstalk suppression circuit included in the second data communication circuit, the second crosstalk suppression circuit being configured to suppress crosstalk between a transmitter and a receiver of the second data communication circuit; and
after completing adjustment of the capacitance of the second crosstalk suppression circuit:
providing a first calibration signal from the first data communication circuit to the second data communication circuit, the first calibration signal being based on a clock signal of the first data communication circuit;
providing a second calibration signal from the second data communication circuit to the first data communication circuit, the second calibration signal being based on a clock signal of the first data communication circuit;
determining, by the first data communication circuit, based on the second calibration signal:
a threshold of a comparator included in the receiver of the first data communication circuit; and
a clock recovery delay for a decoder of the first data communication circuit; and

determining, by the second data communication circuit, based on the first calibration signal:
a threshold of a comparator included in the receiver of the second data communication circuit; and
a clock recovery delay for a decoder of the second data commun

Assignees

• Semiconductor Components Ind Llc

Inventors

• Rehman Syed Enam
• Constantino John

Classifications

• H04B3/34

  by systematic interconnection of lengths of cable during laying; by addition of balancing components to cable during laying · CPC title

• H04L25/085

  Arrangements for reducing interference in line transmission systems, e.g. by differential transmission · CPC title

• H04L27/06

  Demodulator circuits; Receiver circuits · CPC title

• H04B1/40 Primary

  Circuits · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title