Isolation between semiconductor components

Patent metadata

Field	Value
Publication number	US-9735112-B2
Application number	US-201514593642-A
Country	US
Kind code	B2
Filing date	Jan 9, 2015
Priority date	Jan 10, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.

First claim

What is claimed is:

1. An apparatus comprising:
a first lead frame portion;
a second lead frame portion;
a first semiconductor die, the first semiconductor die being in a flip-chip configuration;
a second semiconductor die; and
an isolation substrate bridge including a dielectric substrate, the dielectric substrate having a first surface, a second surface, a first end portion, and a second end portion, the first end portion being coupled to the first lead frame portion, the second end portion being coupled to the second lead frame portion, the isolation substrate bridge being disposed outside of the first semiconductor die and the second semiconductor die,
the first semiconductor die, the second semiconductor die, and the isolation substrate bridge being included in a molding of a semiconductor package, the first semiconductor die being coupled to the first surface of the dielectric substrate via a conductive component, the second semiconductor die being coupled to the first surface of the dielectric substrate,
the isolation substrate bridge including a pair of conductive transmission lines disposed on the second surface of the dielectric substrate, the pair of conductive transmission lines being separated from the conductive component by a thickness of the isolation substrate bridge.

2. The apparatus of claim 1 , wherein the isolation substrate bridge is configured to transmit data between the first semiconductor die and the second semiconductor die via the pair of conductive transmission lines.

3. The apparatus of claim 1 , wherein the dielectric substrate includes one of a glass material and a ceramic material.

4. The apparatus of claim 1 , wherein the isolation substrate bridge includes a dielectric thickness that provides a distance through insulation equal to or greater than 0.1 mm.

5. The apparatus of claim 1 , wherein the isolation substrate bridge defines a distance through insulation that is at least twice a thickness of the isolation substrate bridge, the twice the thickness being greater than or equal to a minimum distance between the first semiconductor die and the second semiconductor die.

6. The apparatus of claim 1 , wherein the pair of conductive transmission lines define a differential communication channel for communicating between the first semiconductor die and the second semiconductor die.

7. The apparatus of claim 1 , wherein at least one of the first semiconductor die and the second semiconductor die includes a top conductive layer and a bottom conductive layer, wherein the isolation substrate bridge is formed outside the top conductive layer and the bottom conductive layer.

8. An apparatus comprising:
a first lead frame;
a second lead frame, the second lead frame being separated from the first lead frame by a distance;
a first semiconductor die;
a second semiconductor die;
an isolation substrate bridge including a dielectric substrate and a pair of conductive transmission lines, the dielectric substrate having a first surface, a second surface, a first end portion, and a second end portion, the first end portion being coupled to the first lead frame, the second end portion being coupled to the second lead frame,
the first semiconductor die and the second semiconductor die being coupled to the first surface of the dielectric substrate, the pair of conductive transmission lines being coupled to the second surface of the dielectric substrate; and
a conductive component coupled to the second lead frame and the second semiconductor die, the conductive component extending along a portion of the second surface between the second lead frame and the second semiconductor die,
the isolation substrate bridge defining a distance through insulation that is at least twice a thickness of the isolation substrate bridge, the twice the thickness being greater than or equal to a distance between the first semiconductor die and the second semiconductor die.

9. An apparatus comprising:
a first semiconductor die;
a second semiconductor die, the first semiconductor die being in a flip-chip configuration; and
an isolation substrate bridge coupled to the first semiconductor die and the second semiconductor die, the isolation substrate bridge configured to support communication between the first semiconductor die and the second semiconductor die;
a molding compound disposed on a first surface of the isolation substrate bridge such that the molding compound encloses the first semiconductor die and the second semiconductor die;
at least one conductive transmission line coupled to a second surface of the isolation substrate bride; and
a plurality of stacks disposed on an end portion of the isolation substrate bridge, each stack of the plurality of stacks being coupled to a different terminal of the first semiconductor die via a separate trace, each stack of the plurality of stacks having a portion that protrudes outward from an outer surface of the molding compound.

10. The apparatus of claim 9 , wherein the isolation substrate bridge includes a differential communication channel for communicating between the first semiconductor die and the second semiconductor die.

11. The apparatus of claim 9 , wherein at least one of the first semiconductor die and the second semiconductor die includes a top conductive layer and a bottom conductive layer, wherein the isolation substrate bridge is formed outside the top conductive layer and the bottom conductive layer.

12. The apparatus of claim 1 , further comprising:
a first conductive component coupled to the first lead frame portion and the first semiconductor die, the first conductive component having a portion that is disposed between the first lead frame portion and the first end portion of the isolation substrate bridge, the first conductive component extending along a portion of the second surface of the dielectric substrate between the first lead frame portion and the first semiconductor die;
a second conductive component coupled to the second lead frame portion and the second semiconductor die, the second conductive component having a portion that is disposed between the second lead frame portion and the second end portion of the isolation substrate bridge, the second conductive component extending along a portion of the second surface of the dielectric substrate between the second lead frame portion and the second semiconductor die.

13. The apparatus of claim 1 , wherein the isolation substrate bridge includes a secondary pair of conductive transmission lines disposed on the second surface of the dielectric substrate, wherein the pair of conducive transmission lines and the secondary pair of conductive transmission lines define a bi-directional communication channel.

14. The apparatus of claim 1 , wherein the conductive component is a first conductive bump, and the first semiconductor die is coupled to the isolation substrate bridge with the first conductive bump and a second conductive bump, the first conductive bump disposed apart from the second conductive bump.

15. The apparatus of claim 8 , further comprising:
a secondary conductive component coupled to the first lead frame and the first semiconductor die, the secondary conductive component extending along a portion of the second surface between the first lead frame and the first semiconductor die.

16. The apparatus of claim 8 , wherein the second semiconductor die is coupled to the isolation substrate bridge via a first conductive bump and a second conductive bump, wherein the conductive component is coupled to the second conductive bump and extends along the portion of the sec

Assignees

• Fairchild Semiconductor

Inventors

• Constantino John
• Luk Timwah
• Ashrafzadeh Ahmad
• Krause Robert L
• Shacham Etan
• Quinones Maria Clemens Ypil
• Bryzek Janusz
• Wu Chung-Lin

Classifications

• H10W90/759

  between a chip and a laterally-adjacent discrete passive device · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/738

  between a chip and a stacked discrete passive device · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title