Converter topology with adaptive power path architecture

US10404175B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10404175-B2
Application numberUS-201715859031-A
CountryUS
Kind codeB2
Filing dateDec 29, 2017
Priority dateDec 29, 2017
Publication dateSep 3, 2019
Grant dateSep 3, 2019

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In described examples, a DC-DC converter provides electrical power. In response to an input voltage falling below a high voltage operation threshold, the converter repeatedly performs a first normal (N) phase and a second N phase. The first N phase includes delivering power through an inductor from the input voltage. The second N phase includes coupling an input terminal of the inductor to a ground. In response to the input voltage rising above a normal operation threshold, the converter performs a first high voltage (HV) phase, then a second HV phase, then a third HV phase, then the second HV phase, and then repeats from the first HV phase. The first HV phase includes delivering power through the inductor from the input voltage and charging a flying capacitor. The second HV phase includes coupling the input terminal of the inductor to the ground. The third HV phase includes delivering power through the inductor by discharging the flying capacitor through the inductor.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of providing electrical power using a DC-DC converter, the method comprising: in response to an input voltage falling below a high voltage operation threshold, repeatedly performing a first normal phase and a second normal phase, the first normal phase including delivering power through an inductor from the input voltage, and the second normal phase including coupling an input terminal of the inductor to a ground; and in response to the input voltage rising above a normal operation threshold, performing a first high voltage phase, then a second high voltage phase, then a third high voltage phase, then the second high voltage phase, and then repeating from the first high voltage phase, the first high voltage phase including delivering power through the inductor from the input voltage and charging a flying capacitor, the second high voltage phase including coupling the input terminal of the inductor to the ground, and the third high voltage phase including delivering power through the inductor by discharging the flying capacitor through the inductor. 2. The method of claim 1 , wherein the first normal phase, the first high voltage phase and the third high voltage phase each have a duty cycle equal to an output voltage divided by the input voltage. 3. The method of claim 1 , wherein a voltage across the flying capacitor during at least one of the high voltage phases is at least one half of the input voltage. 4. A method of providing electrical power using a DC-DC converter, the method comprising: a) coupling an input terminal of an inductor to an input voltage instead of a ground; b) coupling the input terminal to the ground instead of the input voltage; c) coupling a top plate of a capacitor to the input voltage and a bottom plate of the capacitor to the input terminal, and decoupling the bottom plate and the input terminal from the ground; d) decoupling the top plate from the input voltage and the input terminal, and coupling the bottom plate and the input terminal to the ground; e) coupling the top plate to the input terminal, coupling the bottom plate to the ground, and decoupling the input terminal from the ground; f) in response to the input voltage falling below a high voltage operation threshold, repeatedly performing the steps a) and b), until after the input voltage rises above a normal operation threshold; and g) in response to the input voltage rising above the normal operation threshold, repeatedly performing the steps c) then d) then e) then d), until after the input voltage falls below the high voltage operation threshold; the steps a), b), c), d) and e) each including coupling an output terminal of the inductor to the ground. 5. The method of claim 4 , wherein a voltage across the capacitor during the steps c), d) and e) is at least half the input voltage. 6. The method of claim 4 , wherein during the steps c), d) and e), a voltage across each of multiple switches controlling the coupling and decoupling is less than the normal operation threshold. 7. The method of claim 4 , wherein a maximum of the input voltage during the step g) is at least double a maximum of the input voltage during the step f). 8. The method of claim 4 , further comprising transitioning from the step g) to the step f) in response to the input voltage falling below the high voltage operation threshold, the transitioning including charging the capacitor to the input voltage during the repetitions of the step d). 9. The method of claim 4 , further comprising, in response to the input voltage rising above the normal operation threshold, discharging the capacitor by repeatedly performing the steps c) and d) until after the capacitor is at a selected fraction of the input voltage. 10. The method of claim 9 , wherein in response to the capacitor is discharged to the selected fraction of the input voltage, the repeatedly performing ceases, and the step g) is performed. 11. A DC-DC converter, comprising: first, second, third, fourth and fifth switches having respective control terminals; a first node coupled between the first and second switches, the first node adapted to be coupled to a top plate of a capacitor; a second node coupled between the third and fifth switches, the second node adapted to be coupled to a bottom plate of the capacitor; a third node coupled between the second and third switches, the third node adapted to be coupled to an input terminal of an inductor; an input node, the first switch coupled between the input node and the first node; a ground node, the fifth switch coupled between the ground node and the second node, and the fourth switch coupled between the ground node and the third node; control circuitry coupled to the input node and to the control terminals, the control circuitry configured to switch the control terminals in a normal mode in response to a voltage at the input node falling below a high voltage operation threshold, and in a high voltage mode in response to the voltage at the input node rising above a normal operation threshold; the control circuitry configured to repeatedly switch the control terminals between a first normal phase and a second normal phase during the normal mode, wherein: in the first and second normal phases, the first switch is closed and the fifth switch is closed; in the first normal phase, the second switch is closed, and the third and fourth switches are open; and in the second normal phase, the second and third switches are open, and the fourth switch is closed; and the control circuitry configured to repeatedly switch the control terminals between a first high voltage phase, then a second high voltage phase, then a third high voltage phase and then the second high voltage phase, during the high voltage mode, wherein: in the first high voltage phase, the first switch is closed, the third switch is closed, and the second, fourth and fifth switches are open; in the second high voltage phase, the third, fourth and fifth switches are closed, and the first and second switches are open; and in the third high voltage phase, the second switch is closed, and the fifth switch is closed, and the first, third and fourth switches are open. 12. The converter of claim 11 , wherein the first, second, third, fourth and fifth switches are rated for operation at less than or equal to the normal operation threshold. 13. The converter of claim 11 , wherein the capacitor is rated for operation at less than or equal to the normal operation threshold. 14. The converter of claim 11 , wherein during at least one of the high voltage phases, a voltage across each of the first, second, third, fourth and fifth switches is less than half the voltage at the input node. 15. The converter of claim 11 , further comprising an auxiliary charging circuit coupled to the control circuitry and adapted to be coupled to the capacitor, the control circuitry configured to cause the auxiliary charging circuit to charge the capacitor during repetitions of the second normal phase, in response to the voltage at the input node falling below the high voltage operation threshold and before a voltage across the capacitor equals the voltage at the input node. 16. The converter of claim 11 , wherein the control circuitry is configured to transition the control terminals from the normal mode to the high voltage mode, in response to the voltage at the input node rising above the normal operation threshold, the transition including repeatedly performing the first high voltage phase and the second high voltage phase. 17. The converter of claim 16 , whe

Assignees

Inventors

Classifications

  • including plural semiconductor devices as final control devices for a single load · CPC title

  • Means for starting or stopping converters · CPC title

  • H02M3/1588Primary

    comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence) · CPC title

  • for the simultaneous control of series or parallel connected semiconductor devices · CPC title

  • Electricity · mapped topic

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What does patent US10404175B2 cover?
In described examples, a DC-DC converter provides electrical power. In response to an input voltage falling below a high voltage operation threshold, the converter repeatedly performs a first normal (N) phase and a second N phase. The first N phase includes delivering power through an inductor from the input voltage. The second N phase includes coupling an input terminal of the inductor to a gr…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H02M3/1588. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 03 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).