Memory cell and an array of memory cells

Patent metadata

Field	Value
Publication number	US-10553595-B2
Application number	US-201816007054-A
Country	US
Kind code	B2
Filing date	Jun 13, 2018
Priority date	Jun 16, 2014
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.

First claim

The invention claimed is:

1. A memory cell, comprising:
a first electrode and a second electrode;
a select device and a programmable device in series with each other between the first and second electrodes, the select device being proximate and electrically coupled to the first electrode, the programmable device being proximate and electrically coupled to the second electrode; and
the programmable device comprising:
a radially inner electrode having radially outer sidewalls;
ferroelectric material, all of the ferroelectric material that is in all of the programmable device being radially outward of the radially outer sidewalls of the radially inner electrode;
a radially outer electrode radially outward of the ferroelectric material; and
one of the radially outer electrode or the radially inner electrode being electrically coupled to the select device, the other of the radially outer electrode and the radially inner electrode being electrically coupled to the second electrode, the ferroelectric material and the radially inner electrode having elevationally coincident elevationally outermost surfaces.

2. The memory cell of claim 1 wherein the elevationally coincident elevationally outermost surfaces of the ferroelectric material and the radially inner electrode are horizontally planar.

3. The memory cell of claim 1 wherein the first electrode comprises one horizontally elongated line and the second electrode comprises another horizontally elongated line.

4. The memory cell of claim 1 wherein the radially inner electrode overall is wider at its top than at its bottom.

5. The memory cell of claim 1 wherein the radially outer electrode overall is wider at its top than at its bottom.

6. The memory cell of claim 1 wherein the ferroelectric material overall is wider at its top than at its bottom.

7. The memory cell of claim 1 wherein,
the radially inner electrode overall is wider at its top than at its bottom;
the radially outer electrode overall is wider at its top than at its bottom; and
the ferroelectric material overall is wider at its top than at its bottom.

8. A memory cell, comprising:
a first upper electrode and a second lower electrode;
a select device and a programmable device in series with each other between the first and second electrodes, the select device being directly electrically coupled to the first upper electrode, the programmable device being directly electrically coupled to the second lower electrode; and
the programmable device comprising:
a radially inner electrode having radially outer sidewalls;
ferroelectric material, all of the ferroelectric material that is in all of the programmable device being radially outward of the radially outer sidewalls of the radially inner electrode; and
a radially outer electrode radially outward of the ferroelectric material.

9. The memory cell of claim 8 wherein the radially inner electrode overall is wider at its top than at its bottom.

10. The memory cell of claim 8 wherein the radially outer electrode overall is wider at its top than at its bottom.

11. The memory cell of claim 8 wherein the ferroelectric material overall is wider at its top than at its bottom.

12. The memory cell of claim 8 wherein,
the radially inner electrode overall is wider at its top than at its bottom;
the radially outer electrode overall is wider at its top than at its bottom; and
the ferroelectric material overall is wider at its top than at its bottom.

Assignees

• Micron Technology Inc

Inventors

• Ramaswamy Durai Vishak Nirmal
• Kinney Wayne
• Tiburzi Marco Domenico

Classifications

• G11C11/24

  using capacitors (G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40) · CPC title

• G11C11/21

  using electric elements · CPC title

• H01L27/11507 Primary

  Electricity · mapped topic

• H01L27/11514

  Electricity · mapped topic

• H10D1/716

  having vertical extensions · CPC title