Memory cells comprising ferroelectric material and including current leakage paths having different total resistances

Patent metadata

Field	Value
Publication number	US-10396145-B2
Application number	US-201715404576-A
Country	US
Kind code	B2
Filing date	Jan 12, 2017
Priority date	Jan 12, 2017
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

First claim

The invention claimed is:

1. A memory cell, comprising:
a capacitor comprising:
a first capacitor electrode having laterally-spaced walls that individually have a top surface;
a second capacitor electrode laterally between the walls of the first capacitor electrode, the second capacitor electrode comprising a portion above the first capacitor electrode; and
ferroelectric material laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode, the capacitor comprising an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material; and

a parallel current leakage path between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode, the parallel current leakage path being circuit-parallel with the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path.

2. The memory cell of claim 1 wherein the first capacitor electrode comprises a bottom extending laterally to and between the laterally-spaced walls.

3. The memory cell of claim 1 wherein the elevationally-inner surface is an elevationally-innermost surface of the portion of the second capacitor electrode that is above the first capacitor electrode.

4. The memory cell of claim 1 wherein the parallel current leakage path is between the elevationally-inner surface and both top surfaces of the laterally-spaced walls of the first capacitor electrode.

5. The memory cell of claim 1 wherein the parallel current leakage path is configured so that current there-through when the memory cell is idle is no more than one nanoampere.

6. The memory cell of claim 1 wherein the parallel current leakage path has a dominant band gap of 0.4 eV to 5.0 eV.

7. The memory cell of claim 6 wherein the parallel current leakage path has a dominant band gap that is less than dominant band gap of the ferroelectric material.

8. The memory cell of claim 1 wherein, in operation, any voltage differential across the capacitor when idle is such that any electric field in the ferroelectric material is at least 20 times lower than the intrinsic coercive field of the ferroelectric material.

9. The memory cell of claim 1 wherein the parallel current leakage path comprises a non-linear resistor between the first and second capacitor electrodes exhibiting higher resistance at higher voltages than at lower voltages.

10. The memory cell of claim 1 wherein the parallel current leakage path has minimum length greater than minimum thickness of the ferroelectric material between the first and second capacitor electrodes.

11. The memory cell of claim 1 wherein the dominant band gap of the ferroelectric material is equal to or less than that of the parallel current leakage path.

12. The memory cell of claim 1 wherein the parallel current leakage path predominantly comprises one or more of amorphous silicon, polycrystalline silicon, and germanium.

13. The memory cell of claim 1 wherein the parallel current leakage path predominantly comprises one or more chalcogenides.

14. The memory cell of claim 1 wherein the parallel current leakage path predominantly comprises one or more of silicon-rich silicon nitride, silicon-rich silicon oxide, and intrinsically dielectric material doped with conductivity increasing dopants.

15. The memory cell of claim 1 wherein the parallel current leakage path where between the first and second capacitor electrodes is homogenous.

16. The memory cell of claim 1 wherein the parallel current leakage path where between the first and second capacitor electrodes is non-homogenous.

17. The memory cell of claim 1 wherein the parallel current leakage path is directly against the ferroelectric material.

18. The memory cell of claim 1 wherein the parallel current leakage path is not directly against the ferroelectric material.

19. The memory cell of claim 1 comprising a select device electrically coupled in series with the capacitor.

20. The memory cell of claim 19 wherein, in operation, the select device exhibits currents leakage when the memory cell is idle, the parallel current leakage path being configured so that current there-through when the memory cell is idle is greater than or equal to said current leakage of the select device when the memory cell is idle.

21. The memory cell of claim 20 wherein the parallel current leakage path is configured so that current there-through when the memory cell is idle is no more than one nanoampere.

22. A memory cell, comprising:
a capacitor comprising:
a first capacitor electrode;
a second capacitor electrode comprising a portion above the first capacitor electrode; and
ferroelectric material between the second capacitor electrode and the first capacitor electrode, the capacitor comprising an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material; and

a parallel current leakage path between the second capacitor electrode and the first capacitor electrode; the parallel current leakage path being circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprising an annulus.

23. The memory cell of claim 22 wherein the first capacitor electrode comprises an annulus.

24. The memory cell of claim 23 wherein the annulus of the first capacitor electrode is directly against material of the parallel current leakage path that is in the shape of the annulus of the parallel current leakage path.

25. The memory cell of claim 24 wherein a longitudinal end of the annulus of the first capacitor electrode and a longitudinal end of the annulus of the material of the parallel current leakage path are directly against one another.

26. The memory cell of claim 23 wherein the ferroelectric material comprises an annulus laterally inside the first electrode.

27. A memory cell, comprising:
a capacitor comprising:
a first capacitor electrode;
a second capacitor electrode; and
ferroelectric material between the second capacitor electrode and the first capacitor electrode, the capacitor comprising an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material; and

a circuit-parallel current leakage path between the second capacitor electrode and the first capacitor electrode, the circuit-parallel current leakage path being circuit-parallel with the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path, the circuit-parallel current leakage path being physically-parallel and alongside the ferroelectric material from a bottom surface to a top surface of material of the circuit-parallel current leakage path.

28. The memory cell of claim 27 wherein the circuit-parallel current leakage path is directly against the ferroelectric material.

29. The memory cell of claim 28 wherein the circuit-parallel current leakage path is directly against the ferroelectric material from the bottom surface to the top surface of the material of the circuit-p

Assignees

• Micron Technology Inc

Inventors

• Balakrishnan Muralikrishnan
• Cook Beth R
• Ramaswamy Durai Vishak Nirmal

Classifications

• H01L28/75

  Electricity · mapped topic

• H01L28/65 Primary

  Electricity · mapped topic

• H01L27/11507

  Electricity · mapped topic

• H01L28/91

  Electricity · mapped topic

• H10D1/716

  having vertical extensions · CPC title