Substrate and semiconductor device package

Patent metadata

Field	Value
Publication number	US-10553527-B2
Application number	US-201715702700-A
Country	US
Kind code	B2
Filing date	Sep 12, 2017
Priority date	Sep 12, 2017
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

A substrate including a dielectric layer and a patterned conductive layer adjacent to the dielectric layer is provided. The patterned conductive layer comprises a first conductive pad, the first conductive pad comprises a first portion having a first concave sidewall. The substrate further includes a protection layer disposed on the patterned conductive layer, and the protection layer covers the first portion of the first conductive pad.

First claim

What is claimed is:

1. A substrate, comprising:
a dielectric layer;
a patterned conductive layer adjacent to the dielectric layer, the patterned conductive layer comprising a first conductive pad, the first conductive pad comprising a first portion having a first concave sidewall, the first concave sidewall constituting an outer wall of the first conductive pad; and
a protection layer disposed on the patterned conductive layer and covering the first portion of the first conductive pad.

2. The substrate of claim 1 , wherein the patterned conductive layer further comprises a second conductive pad under the first conductive pad.

3. The substrate of claim 2 , wherein a width of the second conductive pad is different from a width of the first conductive pad.

4. The substrate of claim 2 , wherein a width of the second conductive pad is greater than a width of the first conductive pad.

5. The substrate of claim 2 , wherein the protection layer comprises a step structure.

6. The substrate of claim 2 , wherein the protection layer surrounds the first conductive pad.

7. The substrate of claim 2 , wherein the protection layer is in contact with at least a portion of a sidewall of the first conductive pad.

8. The substrate of claim 1 , further comprising a first area configured to receive a semiconductor device, wherein the first conductive pad is disposed within the first area.

9. The substrate of claim 8 , wherein the patterned conductive layer further comprises a second conductive pad, the second conductive pad comprises a first portion having a first concave sidewall, and the protection layer covers the first portion of the second conductive pad, and wherein the first area has a geometric center, and wherein the first concave sidewall of the first conductive pad faces the geometric center and wherein the first concave sidewall of the second conductive pad faces the geometric center.

10. The substrate of claim 9 , wherein a curvature center of the first concave sidewall of the first conductive pad and a curvature center of the first concave sidewall of the second conductive pad are concentric.

11. The substrate of claim 8 , wherein the first conductive pad is disposed adjacent to a corner of the first area.

12. The substrate of claim 8 , wherein the first area has a geometric center, and wherein the first conductive pad further comprises a first convex sidewall, and a distance from the first convex sidewall to the geometric center is greater than a distance from the first concave sidewall to the geometric center.

13. The substrate of claim 12 , wherein a curvature center of the first convex sidewall and a curvature center of the first concave sidewall are non-concentric.

14. The substrate of claim 12 , wherein a curvature center of the first convex sidewall and a curvature center of the first concave sidewall are concentric.

15. A semiconductor device package, comprising:
a substrate comprising:
a dielectric layer; and
a patterned conductive layer adjacent to the dielectric layer, the patterned conductive layer comprising a first conductive pad, the first conductive pad comprising a first portion having a concave sidewall, the concave sidewall constituting an outer wall of the first conductive pad;
a protection layer disposed on the patterned conductive layer and covering the first portion of the first conductive pad; and

a semiconductor device on the substrate and electrically connected to the first conductive pad of the patterned conductive layer.

16. The semiconductor device package of claim 15 , further comprising a conductive connection element electrically connected between the semiconductor device and the first conductive pad of the patterned conductive layer.

17. The semiconductor device package of claim 15 , wherein the protection layer comprises a resin and fillers.

18. The semiconductor device package of claim 15 , wherein the protection layer comprises a resin.

19. The semiconductor device package of claim 15 , wherein the semiconductor device has a dimension equal to or greater than about 450 square millimeter (mm 2 ).

20. The semiconductor device package of claim 15 , wherein the first conductive pad further comprises a convex sidewall, and wherein the concave sidewall has a curvature center and the convex sidewall has a curvature center, and the curvature center of the concave sidewall and the curvature center of the convex sidewall are disposed at a same side of the first conductive pad.

21. The semiconductor device package of claim 15 , wherein the substrate further comprises a first area configured to receive the semiconductor device, and wherein the first conductive pad is disposed within the first area.

22. The semiconductor device package of claim 21 , wherein the patterned conductive layer further comprises a second conductive pad, the second conductive pad comprises a first portion having a concave sidewall, and wherein the first area has a geometric center, and wherein the concave sidewall of the first conductive pad faces the geometric center and wherein the concave sidewall of the second conductive pad faces the geometric center.

23. The semiconductor device package of claim 22 , wherein a curvature center of the concave sidewall of the first conductive pad and a curvature center of the concave sidewall of the second conductive pad are concentric.

24. The semiconductor device package of claim 21 , wherein the first conductive pad is disposed adjacent to a corner of the first area.

25. The semiconductor device package of claim 21 , wherein the first area has a geometric center, and wherein the first conductive pad further comprises a convex sidewall, and a distance from the convex sidewall of the first conductive pad to the geometric center is greater than a distance from the concave sidewall of the first conductive pad to the geometric center.

Assignees

• Advanced Semiconductor Eng

Inventors

• Chen Dao-Long
• Hung Chih-Pin

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07253

  changes in shapes · CPC title

• H10W72/07252

  changes in structures or sizes · CPC title