Forming interconnects with self-assembled monolayers

Patent metadata

Field	Value
Publication number	US-10553477-B2
Application number	US-201515773158-A
Country	US
Kind code	B2
Filing date	Dec 4, 2015
Priority date	Dec 4, 2015
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

Embodiments of the disclosure are directed to using a SAM liner to promote electroless deposition of metal for integrated circuit interconnects. The SAM liner can be formed on a dielectric substrate. A protective layer can be formed on the SAM liner. The protective layer can double as a seed layer for electroless deposition of an interconnect metal. The interconnect metal can be deposited on the protective layer using electroless deposition. The dielectric, with the SAM liner, the protective layer, and the interconnect metal can be annealed to reflow the interconnect metal into trenches formed in the dielectric.

First claim

The invention claimed is:

1. A device comprising:
a substrate comprising a trench in a dielectric material;
a self-assembled monolayer (SAM) over at least a portion of a bottom of the trench and in contact with the dielectric material in the trench; and
an interconnect material, the SAM residing between the dielectric material and the interconnect material.

2. The device of claim 1 , wherein the interconnect material comprises one of cobalt, ruthenium, platinum, palladium, tungsten, iridium, rhenium or nickel.

3. The device of claim 1 , further comprising a protective material residing between the SAM and the interconnect material.

4. The device of claim 3 , wherein the protective material comprises doped cobalt and the interconnect material comprises pure cobalt.

5. The device of claim 1 , wherein the SAM comprises carbon.

6. The device of claim 1 , wherein the dielectric comprises silicon oxide.

7. The device of claim 1 , wherein at least one dimension of the trench is below 10 nanometers.

8. The device of claim 7 , wherein the at least one dimension is a width.

9. The device of claim 1 , wherein the SAM comprises siloxane.

10. The device of claim 1 , wherein the SAM comprises siloxane terminated with a thiol.

11. The device of claim 1 , wherein the SAM comprises siloxane terminated with a carboxylate salt.

12. The device of claim 1 , wherein the SAM comprises siloxane terminated with an amino radical.

13. The device of claim 1 , wherein the SAM comprises siloxane terminated with an aniline.

14. The device of claim 1 , wherein the SAM comprises siloxane terminated with a metal atom.

15. The device of claim 1 , wherein the SAM comprises siloxane terminated with a Pyridyl.

16. The device of claim 1 , wherein:
the SAM lines sidewalls and the bottom of the trench,
the device further includes a protective material that lines the sidewalls and the bottom of the trench lined with the SAM so that the SAM is between the protective material and the dielectric material, and
the interconnect material is in a gap formed by the protective material lining the sidewalls and the bottom of the trench lined with the SAM.

17. The device of claim 16 , wherein a width of a portion of the gap that is closest to the bottom of the trench is greater than a width of a portion of the gap that is at a top of the trench.

18. The device of claim 16 , wherein the protective material includes a first metal, the interconnect material includes a second metal, and the first metal is less conductive than the second metal.

19. A computing device comprising:
a processor mounted on a substrate;
a communications logic unit within the processor;
a memory within the processor; and
an integrated circuit, the integrated circuit comprising:

a substrate comprising a layer of dielectric material forming a trench;
a self-assembled monolayer (SAM) over at least a portion of a bottom of the trench and in contact with the dielectric material in the trench;
an interconnect material, the SAM residing between the dielectric material and the interconnect material; and
a protective material residing between the SAM and the interconnect material;
wherein the dielectric material comprises silicon oxide.

20. The computing device of claim 19 , wherein the interconnect material comprises one of cobalt, ruthenium, platinum, palladium, tungsten, iridium, rhenium or nickel.

21. The computing device of claim 19 , wherein the protective material comprises doped cobalt and the interconnect material comprises pure cobalt.

22. The computing device of claim 19 , wherein the SAM comprises carbon.

23. The computing device of claim 19 , wherein at least one dimension of the trench is below 10 nanometers.

24. The computing device of claim 19 , wherein the SAM comprises siloxane.

25. The computing device of claim 19 , wherein the SAM comprises siloxane terminated with one of a thiol, a carboxylate salt, an aniline, an amino radical, or a metal atom.

Assignees

• Maestre Caro Aranzazu
• Chebiam Ramanan V
• Intel Corp

Inventors

• Maestre Caro Aranzazu
• Chebiam Ramanan V

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4432

  the principal metal being a noble metal, e.g. gold · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title