Semiconductor device and method for manufacturing such a semiconductor device

Patent metadata

Field	Value
Publication number	US-10553437-B2
Application number	US-201815996589-A
Country	US
Kind code	B2
Filing date	Jun 4, 2018
Priority date	Dec 2, 2015
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) forming source regions by applying a first mask with a first and second mask layer and applying an n dopant, forming a well layer by removing such part of the first mask, which is arranged between the two source regions, and applying a p dopant, forming two channel regions by forming a third mask by performing an etching step, by which the first mask layer is farther removed at the openings than the second mask layer, and then removing the second mask layer, wherein the remaining first mask layer forms a third mask and applying a p dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers.

First claim

The invention claimed is:

1. A method of manufacturing a semiconductor device comprising the following steps (a) to (e):
(a) providing a wide bandgap substrate product having a lowly doped layer of a first conductivity type forming a drift layer in the semiconductor device, the substrate product having a first side and a second side opposite to the first side, wherein the lowly doped layer is arranged on the first side,
(b) then forming, in the wide bandgap substrate product on the first side, two source regions of the first conductivity type having a higher doping concentration than the drift layer up to a source region depth, two channel layers of a second conductivity type, which is different from the first conductivity type, having a channel layer depth and surrounding the two source regions in a lateral direction, which direction is parallel to the first side, thereby separating the two source regions from the drift layer in the lateral direction, and at least one well layer of the second conductivity type having a well layer depth, which is at least as large as the channel layer depth, and having a higher doping concentration than the at least one channel layer, wherein the at least one well layer separates the two source regions from the drift layer on a side of the at least one well layer opposite to the first side, wherein the step (b) comprises:
applying a first mask on the first side, the first mask having openings for the creation of the two source regions, which first mask comprises a first mask layer and a second mask layer on top of the first mask layer,
wherein the first mask layer has a higher etching selectivity than the second mask layer,
then applying a first dopant of the first conductivity type for the creation of the two source regions up to the source region depth,
then removing only such part of the first mask, which is arranged between the two source regions, thereby forming a second mask,
applying a second dopant of the second conductivity type for forming the at least one well layer up to the well layer depth,
performing an etching step on the first side, by which etching the first mask layer is farther removed at the openings than the second mask layer,
removing the second mask layer, the remaining first mask layer forming a third mask,
then applying a third dopant of the second conductivity type for forming the two channel layers up to the channel layer depth;

(c) after step (b) applying a fourth mask, which at least covers the two source regions and the two channel layers,
then applying a fourth dopant of the second conductivity type for forming a plug having a plug depth, which is at least as great as the well layer depth, and having a higher doping concentration than the at least one well layer,

(d) after step (c) forming two gate electrodes on the first side, each of which is separated from any doped layer by an insulating layer, and
(e) after step (c) forming a first main electrode as an ohmic contact on the first side, which at least contacts the two source regions and the plug.

2. The method of manufacturing the semiconductor device according to claim 1 , wherein
in step (c) applying the fourth mask is performed such that the fourth mask extends on a part of the at least one well layer adjoining the two source regions such that after step (c) the at least one well layer surrounds the plug in the lateral direction and such that after step (c) the at least one well layer separates the plug from the two source regions.

3. The method of manufacturing the semiconductor device according to claim 1 , wherein
in step (b) the at least one well layer is formed with a doping concentration, which is at least 10 times higher than the doping concentration of the two channel layers.

4. The method of manufacturing the semiconductor device according to claim 1 wherein
in step (b) the at least one well layer is formed with a doping concentration between 1*10 17 and 1*10 21 cm −3 .

5. The method of manufacturing the semiconductor device according to claim 1 , wherein
in step (b) the two channel layers are formed with a doping concentration between 1*10 16 and 1*10 18 cm −3 .

6. The method of manufacturing the semiconductor device according to claim 1 , wherein
in step (c) the plug is formed with a doping concentration between 2*10 17 and 2*10 21 cm −3 .

7. The method of manufacturing the semiconductor device according to claim 1 , wherein in step (b) the at least one well layer and the two channel layers are formed as a common layer having a doping concentration which is low at the first side in a region lateral to the source regions, and which is rising to a higher doping concentration underneath the source regions.

8. The method of manufacturing the semiconductor device according to claim 2 , wherein
the plug is formed with a doping concentration, which is between 10 times and 100 times higher than the doping concentration of the at least one well layer.

9. The method of manufacturing the semiconductor device according to claim 1 , wherein in step (b) the at least one well layer is formed with a doping concentration which is between 10 times and 100 times higher than the doping concentration of the two channel layers.

10. The method of manufacturing the semiconductor device according to claim 1 , wherein in step (b) the at least one well layer is formed with a doping concentration between 1*10 18 and 1*10 20 cm −3 .

11. The method of manufacturing the semiconductor device according to claim 1 , wherein in step (c) the plug is formed with a doping concentration between 1*10 19 and 2*10 21 cm −3 .

Assignees

• Abb Schweiz Ag

Inventors

• Bartolf Holger
• Rahimo Munaf
• Knoll Lars
• Mihaila Andrei
• Minamisawa Renato

Classifications

• H10D64/01366

  the semiconductor being silicon carbide · CPC title

• H10D64/0115

  to silicon carbide · CPC title

• H10P30/22 Primary

  using masks · CPC title

• H01L29/36

  Electricity · mapped topic

• H01L29/7802

  Electricity · mapped topic